Update prebuilt Clang to match Android kernel.
Bug: 132428451
Change-Id: I8f6e2cb23f381fc0c02ddea99b867e58e925e5be
diff --git a/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h b/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h
index 3ad77c5..a995463 100644
--- a/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h
+++ b/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h
@@ -1,9 +1,8 @@
//===- llvm/Target/CodeGenCWrappers.h - CodeGen C Wrappers ------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/linux-x64/clang/include/llvm/Target/GenericOpcodes.td b/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
index 399cea9..e4b452e 100644
--- a/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
+++ b/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
@@ -1,9 +1,8 @@
//===-- GenericOpcodes.td - Opcodes used with GlobalISel ---*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -93,12 +92,14 @@
let hasSideEffects = 0;
}
+// Only supports scalar result types
def G_CONSTANT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$imm);
let hasSideEffects = 0;
}
+// Only supports scalar result types
def G_FCONSTANT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$imm);
@@ -122,31 +123,31 @@
def G_CTLZ : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src);
+ let InOperandList = (ins type1:$src);
let hasSideEffects = 0;
}
def G_CTLZ_ZERO_UNDEF : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src);
+ let InOperandList = (ins type1:$src);
let hasSideEffects = 0;
}
def G_CTTZ : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src);
+ let InOperandList = (ins type1:$src);
let hasSideEffects = 0;
}
def G_CTTZ_ZERO_UNDEF : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src);
+ let InOperandList = (ins type1:$src);
let hasSideEffects = 0;
}
def G_CTPOP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src);
+ let InOperandList = (ins type1:$src);
let hasSideEffects = 0;
}
@@ -255,21 +256,21 @@
// Generic left-shift.
def G_SHL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src1, type0:$src2);
+ let InOperandList = (ins type0:$src1, type1:$src2);
let hasSideEffects = 0;
}
// Generic logical right-shift.
def G_LSHR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src1, type0:$src2);
+ let InOperandList = (ins type0:$src1, type1:$src2);
let hasSideEffects = 0;
}
// Generic arithmetic right-shift.
def G_ASHR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src1, type0:$src2);
+ let InOperandList = (ins type0:$src1, type1:$src2);
let hasSideEffects = 0;
}
@@ -454,6 +455,12 @@
let hasSideEffects = 0;
}
+def G_FCANONICALIZE : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src);
+ let hasSideEffects = 0;
+}
+
//------------------------------------------------------------------------------
// Floating Point Binary ops.
//------------------------------------------------------------------------------
@@ -540,6 +547,51 @@
let hasSideEffects = 0;
}
+// Floating point base-10 logarithm of a value.
+def G_FLOG10 : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+// Floating point ceiling of a value.
+def G_FCEIL : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+// Floating point cosine of a value.
+def G_FCOS : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+// Floating point sine of a value.
+def G_FSIN : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+// Floating point square root of a value.
+// This returns NaN for negative nonzero values.
+// NOTE: Unlike libm sqrt(), this never sets errno. In all other respects it's
+// libm-conformant.
+def G_FSQRT : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+// Floating point floor of a value.
+def G_FFLOOR : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
//------------------------------------------------------------------------------
// Opcodes for LLVM Intrinsics
//------------------------------------------------------------------------------
@@ -649,6 +701,9 @@
// Extract multiple registers specified size, starting from blocks given by
// indexes. This will almost certainly be mapped to sub-register COPYs after
// register banks have been selected.
+// The output operands are always ordered from lowest bits to highest:
+// %bits_0_7:(s8), %bits_8_15:(s8),
+// %bits_16_23:(s8), %bits_24_31:(s8) = G_UNMERGE_VALUES %0:(s32)
def G_UNMERGE_VALUES : GenericInstruction {
let OutOperandList = (outs type0:$dst0, variable_ops);
let InOperandList = (ins type1:$src);
@@ -662,13 +717,40 @@
let hasSideEffects = 0;
}
-/// Concatenate multiple registers of the same size into a wider register.
+// Concatenate multiple registers of the same size into a wider register.
+// The input operands are always ordered from lowest bits to highest:
+// %0:(s32) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8),
+// %bits_16_23:(s8), %bits_24_31:(s8)
def G_MERGE_VALUES : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src0, variable_ops);
let hasSideEffects = 0;
}
+/// Create a vector from multiple scalar registers. No implicit
+/// conversion is performed (i.e. the result element type must be the
+/// same as all source operands)
+def G_BUILD_VECTOR : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src0, variable_ops);
+ let hasSideEffects = 0;
+}
+
+/// Like G_BUILD_VECTOR, but truncates the larger operand types to fit the
+/// destination vector elt type.
+def G_BUILD_VECTOR_TRUNC : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src0, variable_ops);
+ let hasSideEffects = 0;
+}
+
+/// Create a vector by concatenating vectors together.
+def G_CONCAT_VECTORS : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src0, variable_ops);
+ let hasSideEffects = 0;
+}
+
// Intrinsic without side effects.
def G_INTRINSIC : GenericInstruction {
let OutOperandList = (outs);
diff --git a/linux-x64/clang/include/llvm/Target/GlobalISel/RegisterBank.td b/linux-x64/clang/include/llvm/Target/GlobalISel/RegisterBank.td
index 4dfd139..51578b6 100644
--- a/linux-x64/clang/include/llvm/Target/GlobalISel/RegisterBank.td
+++ b/linux-x64/clang/include/llvm/Target/GlobalISel/RegisterBank.td
@@ -1,9 +1,8 @@
//===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index a3d310c..6b0434a 100644
--- a/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -1,9 +1,8 @@
//===- TargetGlobalISel.td - Common code for GlobalISel ----*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -88,6 +87,13 @@
def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
def : GINodeEquiv<G_CTPOP, ctpop>;
+def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
+def : GINodeEquiv<G_FCEIL, fceil>;
+def : GINodeEquiv<G_FCOS, fcos>;
+def : GINodeEquiv<G_FSIN, fsin>;
+def : GINodeEquiv<G_FABS, fabs>;
+def : GINodeEquiv<G_FSQRT, fsqrt>;
+def : GINodeEquiv<G_FFLOOR, ffloor>;
// Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
// complications that tablegen must take care of. For example, Predicates such
diff --git a/linux-x64/clang/include/llvm/Target/GlobalISel/Target.td b/linux-x64/clang/include/llvm/Target/GlobalISel/Target.td
index 6740f40..538ca65 100644
--- a/linux-x64/clang/include/llvm/Target/GlobalISel/Target.td
+++ b/linux-x64/clang/include/llvm/Target/GlobalISel/Target.td
@@ -1,9 +1,8 @@
//===- Target.td - Define GlobalISel rules -----------------*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/linux-x64/clang/include/llvm/Target/Target.td b/linux-x64/clang/include/llvm/Target/Target.td
index 538605a..380e848 100644
--- a/linux-x64/clang/include/llvm/Target/Target.td
+++ b/linux-x64/clang/include/llvm/Target/Target.td
@@ -1,9 +1,8 @@
//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -479,6 +478,7 @@
bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
// If so, make sure to override
// TargetInstrInfo::getInsertSubregLikeInputs.
+ bit variadicOpsAreDefs = 0; // Are variadic operands definitions?
// Does the instruction have side effects that are not captured by any
// operands of the instruction or other flags?
@@ -933,6 +933,15 @@
let AsmString = "";
let hasSideEffects = 0; // Note side effect is encoded in an operand.
}
+def INLINEASM_BR : StandardPseudoInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins variable_ops);
+ let AsmString = "";
+ let hasSideEffects = 0; // Note side effect is encoded in an operand.
+ let isTerminator = 1;
+ let isBranch = 1;
+ let isIndirectBranch = 1;
+}
def CFI_INSTRUCTION : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
@@ -1104,7 +1113,7 @@
let isBranch = 1;
}
def PATCHABLE_OP : StandardPseudoInstruction {
- let OutOperandList = (outs unknown:$dst);
+ let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let usesCustomInserter = 1;
let mayLoad = 1;
@@ -1164,8 +1173,8 @@
let hasSideEffects = 1;
}
def FENTRY_CALL : StandardPseudoInstruction {
- let OutOperandList = (outs unknown:$dst);
- let InOperandList = (ins variable_ops);
+ let OutOperandList = (outs);
+ let InOperandList = (ins);
let AsmString = "# FEntry call";
let usesCustomInserter = 1;
let mayLoad = 1;
@@ -1555,3 +1564,8 @@
// Pull in the common support for the Global ISel DAG-based selector generation.
//
include "llvm/Target/GlobalISel/SelectionDAGCompat.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for Pfm Counters generation.
+//
+include "llvm/Target/TargetPfmCounters.td"
diff --git a/linux-x64/clang/include/llvm/Target/TargetCallingConv.td b/linux-x64/clang/include/llvm/Target/TargetCallingConv.td
index 95d2b42..11ed4f5 100644
--- a/linux-x64/clang/include/llvm/Target/TargetCallingConv.td
+++ b/linux-x64/clang/include/llvm/Target/TargetCallingConv.td
@@ -1,9 +1,8 @@
//===- TargetCallingConv.td - Target Calling Conventions ---*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -160,6 +159,11 @@
/// that the target supports.
class CallingConv<list<CCAction> actions> {
list<CCAction> Actions = actions;
+
+ /// If true, this calling convention will be emitted as externally visible in
+ /// the llvm namespaces instead of as a static function.
+ bit Entry = 0;
+
bit Custom = 0;
}
diff --git a/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td b/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td
index c4b14eb..5623461 100644
--- a/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td
+++ b/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td
@@ -1,35 +1,44 @@
//===- TargetInstrPredicate.td - ---------------------------*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
-// This file defines MCInstPredicate classes and its subclasses.
+// This file defines class MCInstPredicate and its subclasses.
//
-// MCInstPredicate is used to describe constraints on the opcode/operand(s) of
-// an instruction. Each MCInstPredicate class has a well-known semantic, and it
-// is used by a PredicateExpander to generate code for MachineInstr and/or
-// MCInst.
+// MCInstPredicate definitions are used by target scheduling models to describe
+// constraints on instructions.
//
-// MCInstPredicate definitions can be used to construct MCSchedPredicate
-// definitions. An MCSchedPredicate can be used in place of a SchedPredicate
-// when defining SchedReadVariant and SchedWriteVariant used by a processor
-// scheduling model.
-//
-// Here is an example of MCInstPredicate definition:
+// Here is an example of an MCInstPredicate definition in tablegen:
//
// def MCInstPredicateExample : CheckAll<[
// CheckOpcode<[BLR]>,
// CheckIsRegOperand<0>,
// CheckNot<CheckRegOperand<0, LR>>]>;
//
-// Predicate `MCInstPredicateExample` checks that the machine instruction in
-// input is a BLR, and that operand at index 0 is register `LR`.
+// The syntax for MCInstPredicate is declarative, and predicate definitions can
+// be composed together in order to generate more complex constraints.
//
-// That predicate could be used to rewrite the following definition (from
+// The `CheckAll` from the example defines a composition of three different
+// predicates. Definition `MCInstPredicateExample` identifies instructions
+// whose opcode is BLR, and whose first operand is a register different from
+// register `LR`.
+//
+// Every MCInstPredicate class has a well-known semantic in tablegen. For
+// example, `CheckOpcode` is a special type of predicate used to describe a
+// constraint on the value of an instruction opcode.
+//
+// MCInstPredicate definitions are typically used by scheduling models to
+// construct MCSchedPredicate definitions (see the definition of class
+// MCSchedPredicate in llvm/Target/TargetSchedule.td).
+// In particular, an MCSchedPredicate can be used instead of a SchedPredicate
+// when defining the set of SchedReadVariant and SchedWriteVariant of a
+// processor scheduling model.
+//
+// The `MCInstPredicateExample` definition above is equivalent (and therefore
+// could replace) the following definition from a previous ExynosM3 model (see
// AArch64SchedExynosM3.td):
//
// def M3BranchLinkFastPred : SchedPredicate<[{
@@ -37,22 +46,13 @@
// MI->getOperand(0).isReg() &&
// MI->getOperand(0).getReg() != AArch64::LR}]>;
//
-// MCInstPredicate definitions are used to construct MCSchedPredicate (see the
-// definition of class MCSchedPredicate in llvm/Target/TargetSchedule.td). An
-// MCSchedPredicate can be used by a `SchedVar` to associate a predicate with a
-// list of SchedReadWrites. Note that `SchedVar` are used to create SchedVariant
-// definitions.
-//
-// Each MCInstPredicate class has a well known semantic. For example,
-// `CheckOpcode` is only used to check the instruction opcode value.
-//
-// MCInstPredicate classes allow the definition of predicates in a declarative
-// way. These predicates don't require a custom block of C++, and can be used
-// to define conditions on instructions without being bound to a particular
+// The main advantage of using MCInstPredicate instead of SchedPredicate is
+// portability: users don't need to specify predicates in C++. As a consequence
+// of this, MCInstPredicate definitions are not bound to a particular
// representation (i.e. MachineInstr vs MCInst).
//
-// It also means that tablegen backends must know how to parse and expand them
-// into code that works on MCInst (or MachineInst).
+// Tablegen backends know how to expand MCInstPredicate definitions into actual
+// C++ code that works on MachineInstr (and/or MCInst).
//
// Instances of class PredicateExpander (see utils/Tablegen/PredicateExpander.h)
// know how to expand a predicate. For each MCInstPredicate class, there must be
@@ -105,28 +105,50 @@
int SecondIndex = Second;
}
+// Base class for checks on register/immediate operands.
+// It allows users to define checks like:
+// MyFunction(MI->getOperand(Index).getImm()) == Val;
+//
+// In the example above, `MyFunction` is a function that takes as input an
+// immediate operand value, and returns another value. Field `FunctionMapper` is
+// the name of the function to call on the operand value.
+class CheckOperandBase<int Index, string Fn = ""> : MCOperandPredicate<Index> {
+ string FunctionMapper = Fn;
+}
+
// Check that the machine register operand at position `Index` references
// register R. This predicate assumes that we already checked that the machine
// operand at position `Index` is a register operand.
-class CheckRegOperand<int Index, Register R> : MCOperandPredicate<Index> {
+class CheckRegOperand<int Index, Register R> : CheckOperandBase<Index> {
Register Reg = R;
}
// Check if register operand at index `Index` is the invalid register.
-class CheckInvalidRegOperand<int Index> : MCOperandPredicate<Index>;
+class CheckInvalidRegOperand<int Index> : CheckOperandBase<Index>;
// Check that the operand at position `Index` is immediate `Imm`.
-class CheckImmOperand<int Index, int Imm> : MCOperandPredicate<Index> {
+// If field `FunctionMapper` is a non-empty string, then function
+// `FunctionMapper` is applied to the operand value, and the return value is then
+// compared against `Imm`.
+class CheckImmOperand<int Index, int Imm> : CheckOperandBase<Index> {
int ImmVal = Imm;
}
// Similar to CheckImmOperand, however the immediate is not a literal number.
// This is useful when we want to compare the value of an operand against an
// enum value, and we know the actual integer value of that enum.
-class CheckImmOperand_s<int Index, string Value> : MCOperandPredicate<Index> {
+class CheckImmOperand_s<int Index, string Value> : CheckOperandBase<Index> {
string ImmVal = Value;
}
+// Expands to a call to `FunctionMapper` if field `FunctionMapper` is set.
+// Otherwise, it expands to a CheckNot<CheckInvalidRegOperand<Index>>.
+class CheckRegOperandSimple<int Index> : CheckOperandBase<Index>;
+
+// Expands to a call to `FunctionMapper` if field `FunctionMapper` is set.
+// Otherwise, it simply evaluates to TruePred.
+class CheckImmOperandSimple<int Index> : CheckOperandBase<Index>;
+
// Check that the operand at position `Index` is immediate value zero.
class CheckZeroOperand<int Index> : CheckImmOperand<Index, 0>;
@@ -205,13 +227,13 @@
MCStatement Body = body;
}
-// Check that a call to method `Name` in class "XXXGenInstrInfo" (where XXX is
+// Check that a call to method `Name` in class "XXXInstrInfo" (where XXX is
// the name of a target) returns true.
//
// TIIPredicate definitions are used to model calls to the target-specific
// InstrInfo. A TIIPredicate is treated specially by the InstrInfoEmitter
// tablegen backend, which will use it to automatically generate a definition in
-// the target specific `GenInstrInfo` class.
+// the target specific `InstrInfo` class.
//
// There cannot be multiple TIIPredicate definitions with the same name for the
// same target.
@@ -313,7 +335,7 @@
}
// Convenience classes and definitions used by processor scheduling models to
-// describe dependency breaking instructions.
+// describe dependency breaking instructions and move elimination candidates.
let UpdatesOpcodeMask = 1 in {
def IsZeroIdiomDecl : STIPredicateDecl<"isZeroIdiom">;
@@ -323,8 +345,14 @@
} // UpdatesOpcodeMask
+def IsOptimizableRegisterMoveDecl
+ : STIPredicateDecl<"isOptimizableRegisterMove">;
+
class IsZeroIdiomFunction<list<DepBreakingClass> classes>
: STIPredicate<IsZeroIdiomDecl, classes>;
class IsDepBreakingFunction<list<DepBreakingClass> classes>
: STIPredicate<IsDepBreakingDecl, classes>;
+
+class IsOptimizableRegisterMove<list<InstructionEquivalenceClass> classes>
+ : STIPredicate<IsOptimizableRegisterMoveDecl, classes>;
diff --git a/linux-x64/clang/include/llvm/Target/TargetIntrinsicInfo.h b/linux-x64/clang/include/llvm/Target/TargetIntrinsicInfo.h
index 6a92bde..ef571b1 100644
--- a/linux-x64/clang/include/llvm/Target/TargetIntrinsicInfo.h
+++ b/linux-x64/clang/include/llvm/Target/TargetIntrinsicInfo.h
@@ -1,9 +1,8 @@
//===-- llvm/Target/TargetIntrinsicInfo.h - Instruction Info ----*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/linux-x64/clang/include/llvm/Target/TargetItinerary.td b/linux-x64/clang/include/llvm/Target/TargetItinerary.td
index 182054d..b68ed04 100644
--- a/linux-x64/clang/include/llvm/Target/TargetItinerary.td
+++ b/linux-x64/clang/include/llvm/Target/TargetItinerary.td
@@ -1,9 +1,8 @@
//===- TargetItinerary.td - Target Itinierary Description --*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h b/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h
index 40b77c3..f96e353 100644
--- a/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h
+++ b/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h
@@ -1,9 +1,8 @@
//===-- llvm/Target/TargetLoweringObjectFile.h - Object Info ----*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -201,6 +200,12 @@
virtual void emitLinkerFlagsForUsed(raw_ostream &OS,
const GlobalValue *GV) const {}
+ /// If supported, return the section to use for the llvm.commandline
+ /// metadata. Otherwise, return nullptr.
+ virtual MCSection *getSectionForCommandLines() const {
+ return nullptr;
+ }
+
protected:
virtual MCSection *SelectSectionForGlobal(const GlobalObject *GO,
SectionKind Kind,
diff --git a/linux-x64/clang/include/llvm/Target/TargetMachine.h b/linux-x64/clang/include/llvm/Target/TargetMachine.h
index e743e9f..7dd9b99 100644
--- a/linux-x64/clang/include/llvm/Target/TargetMachine.h
+++ b/linux-x64/clang/include/llvm/Target/TargetMachine.h
@@ -1,9 +1,8 @@
//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -201,6 +200,9 @@
bool getO0WantsFastISel() { return O0WantsFastISel; }
void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; }
+ void setGlobalISelAbort(GlobalISelAbortMode Mode) {
+ Options.GlobalISelAbort = Mode;
+ }
void setMachineOutliner(bool Enable) {
Options.EnableMachineOutliner = Enable;
}
@@ -284,18 +286,6 @@
void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
MCSymbol *getSymbol(const GlobalValue *GV) const;
-
- /// True if the target uses physical regs at Prolog/Epilog insertion
- /// time. If true (most machines), all vregs must be allocated before
- /// PEI. If false (virtual-register machines), then callee-save register
- /// spilling and scavenging are not needed or used.
- virtual bool usesPhysRegsForPEI() const { return true; }
-
- /// True if the target wants to use interprocedural register allocation by
- /// default. The -enable-ipra flag can be used to override this.
- virtual bool useIPRA() const {
- return false;
- }
};
/// This class describes a target machine that is implemented with the LLVM
@@ -349,8 +339,37 @@
bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
raw_pwrite_stream *DwoOut, CodeGenFileType FileTYpe,
MCContext &Context);
+
+ /// True if the target uses physical regs at Prolog/Epilog insertion
+ /// time. If true (most machines), all vregs must be allocated before
+ /// PEI. If false (virtual-register machines), then callee-save register
+ /// spilling and scavenging are not needed or used.
+ virtual bool usesPhysRegsForPEI() const { return true; }
+
+ /// True if the target wants to use interprocedural register allocation by
+ /// default. The -enable-ipra flag can be used to override this.
+ virtual bool useIPRA() const {
+ return false;
+ }
};
+/// Helper method for getting the code model, returning Default if
+/// CM does not have a value. The tiny and kernel models will produce
+/// an error, so targets that support them or require more complex codemodel
+/// selection logic should implement and call their own getEffectiveCodeModel.
+inline CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
+ CodeModel::Model Default) {
+ if (CM) {
+ // By default, targets do not support the tiny and kernel models.
+ if (*CM == CodeModel::Tiny)
+ report_fatal_error("Target does not support the tiny CodeModel");
+ if (*CM == CodeModel::Kernel)
+ report_fatal_error("Target does not support the kernel CodeModel");
+ return *CM;
+ }
+ return Default;
+}
+
} // end namespace llvm
#endif // LLVM_TARGET_TARGETMACHINE_H
diff --git a/linux-x64/clang/include/llvm/Target/TargetOptions.h b/linux-x64/clang/include/llvm/Target/TargetOptions.h
index 07ed773..6b76a11 100644
--- a/linux-x64/clang/include/llvm/Target/TargetOptions.h
+++ b/linux-x64/clang/include/llvm/Target/TargetOptions.h
@@ -1,9 +1,8 @@
//===-- llvm/Target/TargetOptions.h - Target Options ------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -96,6 +95,14 @@
SCE // Tune debug info for SCE targets (e.g. PS4).
};
+ /// Enable abort calls when global instruction selection fails to lower/select
+ /// an instruction.
+ enum class GlobalISelAbortMode {
+ Disable, // Disable the abort.
+ Enable, // Enable the abort.
+ DisableWithDiag // Disable the abort but emit a diagnostic on failure.
+ };
+
class TargetOptions {
public:
TargetOptions()
@@ -192,6 +199,10 @@
/// EnableGlobalISel - This flag enables global instruction selection.
unsigned EnableGlobalISel : 1;
+ /// EnableGlobalISelAbort - Control abort behaviour when global instruction
+ /// selection fails to lower/select an instruction.
+ GlobalISelAbortMode GlobalISelAbort = GlobalISelAbortMode::Enable;
+
/// UseInitArray - Use .init_array instead of .ctors for static
/// constructors.
unsigned UseInitArray : 1;
diff --git a/linux-x64/clang/include/llvm/Target/TargetPfmCounters.td b/linux-x64/clang/include/llvm/Target/TargetPfmCounters.td
new file mode 100644
index 0000000..e1d5013
--- /dev/null
+++ b/linux-x64/clang/include/llvm/Target/TargetPfmCounters.td
@@ -0,0 +1,49 @@
+//===- TargetPfmCounters.td - Target Pfm Counters -*- tablegen ----------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the target-independent interfaces for performance counters.
+
+// Definition of a hardware counters from libpfm identifiers.
+class PfmCounter<string counter> {
+ // The name of the counter that measures events.
+ // The name can be "some_counter + some_other_counter", in which case the
+ // measured value is the sum of events on these counters.
+ string Counter = counter;
+}
+
+// Issue counters can be tied to a ProcResource
+class PfmIssueCounter<string resource_name, string counter>
+ : PfmCounter<counter> {
+ // The name of the ProcResource on which uops are issued. This is used by
+ // llvm-exegesis to compare measurements with values in the SchedModels.
+ // If the CPU has a sched model, this should correspond to the name of a
+ // ProcResource.
+ string ResourceName = resource_name;
+}
+
+def NoPfmCounter : PfmCounter <""> {}
+
+// Set of PfmCounters for measuring sched model characteristics.
+class ProcPfmCounters {
+ // Processors can define how to measure cycles by defining a CycleCounter.
+ PfmCounter CycleCounter = NoPfmCounter;
+ // Processors can define how to measure uops by defining a UopsCounter.
+ PfmCounter UopsCounter = NoPfmCounter;
+ // Processors can define how to measure issued uops by defining IssueCounters.
+ list<PfmIssueCounter> IssueCounters = [];
+}
+
+// A binding of a set of counters to a CPU.
+class PfmCountersBinding<string cpu_name, ProcPfmCounters counters> {
+ string CpuName = cpu_name;
+ ProcPfmCounters Counters = counters;
+}
+
+// Declares the default binding for unbound CPUs for the target.
+class PfmCountersDefaultBinding<ProcPfmCounters counters>
+ : PfmCountersBinding<"", counters> {}
diff --git a/linux-x64/clang/include/llvm/Target/TargetSchedule.td b/linux-x64/clang/include/llvm/Target/TargetSchedule.td
index 7d7ce2d..cbfad5f 100644
--- a/linux-x64/clang/include/llvm/Target/TargetSchedule.td
+++ b/linux-x64/clang/include/llvm/Target/TargetSchedule.td
@@ -1,9 +1,8 @@
//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -373,6 +372,10 @@
SchedMachineModel SchedModel = ?;
code Predicate = pred;
}
+
+// Define a predicate to be typically used as the default case in a
+// SchedVariant. It the SchedVariant does not use any other predicate based on
+// MCSchedPredicate, this is the default scheduling case used by llvm-mca.
def NoSchedPred : MCSchedPredicate<TruePred>;
// Associate a predicate with a list of SchedReadWrites. By default,
@@ -460,6 +463,10 @@
// - The number of physical registers which can be used for register renaming
// purpose.
// - The cost of a register rename.
+// - The set of registers that allow move elimination.
+// - The maximum number of moves that can be eliminated every cycle.
+// - Whether move elimination is limited to register moves whose input
+// is known to be zero.
//
// The cost of a rename is the number of physical registers allocated by the
// register alias table to map the new definition. By default, register can be
@@ -506,11 +513,35 @@
// partial write is combined with the previous super-register definition. We
// should add support for these cases, and correctly model merge problems with
// partial register accesses.
+//
+// Field MaxMovesEliminatedPerCycle specifies how many moves can be eliminated
+// every cycle. A default value of zero for that field means: there is no limit
+// to the number of moves that can be eliminated by this register file.
+//
+// An instruction MI is a candidate for move elimination if a call to
+// method TargetSubtargetInfo::isOptimizableRegisterMove(MI) returns true (see
+// llvm/CodeGen/TargetSubtargetInfo.h, and llvm/MC/MCInstrAnalysis.h).
+//
+// Subtargets can instantiate tablegen class IsOptimizableRegisterMove (see
+// llvm/Target/TargetInstrPredicate.td) to customize the set of move elimination
+// candidates. By default, no instruction is a valid move elimination candidate.
+//
+// A register move MI is eliminated only if:
+// - MI is a move elimination candidate.
+// - The destination register is from a register class that allows move
+// elimination (see field `AllowMoveElimination` below).
+// - Constraints on the move kind, and the maximum number of moves that can be
+// eliminated per cycle are all met.
+
class RegisterFile<int numPhysRegs, list<RegisterClass> Classes = [],
- list<int> Costs = []> {
+ list<int> Costs = [], list<bit> AllowMoveElim = [],
+ int MaxMoveElimPerCy = 0, bit AllowZeroMoveElimOnly = 0> {
list<RegisterClass> RegClasses = Classes;
list<int> RegCosts = Costs;
+ list<bit> AllowMoveElimination = AllowMoveElim;
int NumPhysRegs = numPhysRegs;
+ int MaxMovesEliminatedPerCycle = MaxMoveElimPerCy;
+ bit AllowZeroMoveEliminationOnly = AllowZeroMoveElimOnly;
SchedMachineModel SchedModel = ?;
}
@@ -530,30 +561,12 @@
SchedMachineModel SchedModel = ?;
}
-// Allow the definition of hardware counters.
-class PfmCounter {
+// Base class for Load/StoreQueue. It is used to identify processor resources
+// which describe load/store queues in the LS unit.
+class MemoryQueue<ProcResource PR> {
+ ProcResource QueueDescriptor = PR;
SchedMachineModel SchedModel = ?;
}
-// Each processor can define how to measure cycles by defining a
-// PfmCycleCounter.
-class PfmCycleCounter<string counter> : PfmCounter {
- string Counter = counter;
-}
-
-// Each ProcResourceUnits can define how to measure issued uops by defining
-// a PfmIssueCounter.
-class PfmIssueCounter<ProcResourceUnits resource, list<string> counters>
- : PfmCounter{
- // The resource units on which uops are issued.
- ProcResourceUnits Resource = resource;
- // The list of counters that measure issue events.
- list<string> Counters = counters;
-}
-
-// Each processor can define how to measure NumMicroOps by defining a
-// PfmUopsCounter.
-class PfmUopsCounter<string counter> : PfmCounter {
- string Counter = counter;
-}
-
+class LoadQueue<ProcResource LDQueue> : MemoryQueue<LDQueue>;
+class StoreQueue<ProcResource STQueue> : MemoryQueue<STQueue>;
diff --git a/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td b/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
index 4e463b9..174d97a 100644
--- a/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
+++ b/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
@@ -1,9 +1,8 @@
//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -116,12 +115,18 @@
def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
]>;
+def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr
+ SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
+]>;
def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift
SDTCisSameAs<0, 1>, SDTCisInt<2>
]>;
def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
]>;
+def SDTIntScaledBinOp : SDTypeProfile<1, 3, [ // smulfix, umulfix
+ SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
+]>;
def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
@@ -162,7 +167,7 @@
]>;
def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec
SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>,
- SDTCisOpSmallerThanOp<1, 0>, SDTCisSameSizeAs<0,1>
+ SDTCisOpSmallerThanOp<1, 0>
]>;
def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
@@ -259,6 +264,11 @@
def SDTAtomic2 : SDTypeProfile<1, 2, [
SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
]>;
+
+def SDTFPAtomic2 : SDTypeProfile<1, 2, [
+ SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1>
+]>;
+
def SDTAtomicStore : SDTypeProfile<0, 2, [
SDTCisPtrTy<0>, SDTCisInt<1>
]>;
@@ -350,6 +360,8 @@
def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
+def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
+def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
def and : SDNode<"ISD::AND" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def or : SDNode<"ISD::OR" , SDTIntBinOp,
@@ -373,6 +385,14 @@
def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
+def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
+def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
+def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>;
+def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>;
+
+def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>;
+def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>;
+
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;
def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
@@ -406,8 +426,14 @@
[SDNPCommutative, SDNPAssociative]>;
def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
[SDNPCommutative, SDNPAssociative]>;
-def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
-def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
+def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp,
+ [SDNPCommutative]>;
+def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
+ [SDNPCommutative]>;
+def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp,
+ [SDNPCommutative, SDNPAssociative]>;
+def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp,
+ [SDNPCommutative, SDNPAssociative]>;
def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>;
def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
@@ -491,6 +517,11 @@
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_fadd : SDNode<"ISD::ATOMIC_LOAD_FADD" , SDTFPAtomic2,
+ [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2,
+ [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+
def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
@@ -616,6 +647,15 @@
code ImmediateCode = [{}];
SDNodeXForm OperandTransform = xform;
+ // When this is set, the PredicateCode may refer to a constant Operands
+ // vector which contains the captured nodes of the DAG, in the order listed
+ // by the Operands field above.
+ //
+ // This is useful when Fragments involves associative / commutative
+ // operators: a single piece of code can easily refer to all operands even
+ // when re-associated / commuted variants of the fragment are matched.
+ bit PredicateCodeUsesOperands = 0;
+
// Define a few pre-packaged predicates. This helps GlobalISel import
// existing rules from SelectionDAG for many common cases.
// They will be tested prior to the code in pred and must not be used in