Update prebuilt Clang to match Android kernel.
Bug: 132428451
Change-Id: I8f6e2cb23f381fc0c02ddea99b867e58e925e5be
diff --git a/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h b/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h
index 950a1af..dfefd7e 100644
--- a/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h
+++ b/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h
@@ -1,9 +1,8 @@
//===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -136,6 +135,17 @@
return isZeroIdiom(MI, Mask, CPUID);
}
+ /// Returns true if MI is a candidate for move elimination.
+ ///
+ /// Different subtargets may apply different constraints to optimizable
+ /// register moves. For example, on most X86 subtargets, a candidate for move
+ /// elimination cannot specify the same register for both source and
+ /// destination.
+ virtual bool isOptimizableRegisterMove(const MCInst &MI,
+ unsigned CPUID) const {
+ return false;
+ }
+
/// Given a branch instruction try to get the address the branch
/// targets. Return true on success, and the address in Target.
virtual bool