Update prebuilt Clang to match Android kernel.
Bug: 132428451
Change-Id: I8f6e2cb23f381fc0c02ddea99b867e58e925e5be
diff --git a/linux-x64/clang/include/llvm/CodeGen/TargetSubtargetInfo.h b/linux-x64/clang/include/llvm/CodeGen/TargetSubtargetInfo.h
index e28673d..bf0e9b2 100644
--- a/linux-x64/clang/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/linux-x64/clang/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -1,9 +1,8 @@
//===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -169,6 +168,19 @@
return isZeroIdiom(MI, Mask);
}
+ /// Returns true if MI is a candidate for move elimination.
+ ///
+ /// A candidate for move elimination may be optimized out at register renaming
+ /// stage. Subtargets can specify the set of optimizable moves by
+ /// instantiating tablegen class `IsOptimizableRegisterMove` (see
+ /// llvm/Target/TargetInstrPredicate.td).
+ ///
+ /// SubtargetEmitter is responsible for processing all the definitions of class
+ /// IsOptimizableRegisterMove, and auto-generate an override for this method.
+ virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
+ return false;
+ }
+
/// True if the subtarget should run MachineScheduler after aggressive
/// coalescing.
///
@@ -177,9 +189,6 @@
/// TargetLowering preference). It does not yet disable the postRA scheduler.
virtual bool enableMachineScheduler() const;
- /// Support printing of [latency:throughput] comment in output .S file.
- virtual bool supportPrintSchedInfo() const { return false; }
-
/// True if the machine scheduler should disable the TLI preference
/// for preRA scheduling with the source level scheduler.
virtual bool enableMachineSchedDefaultSched() const { return true; }
@@ -273,10 +282,6 @@
/// possible.
virtual bool enableSubRegLiveness() const { return false; }
- /// Returns string representation of scheduler comment
- std::string getSchedInfoStr(const MachineInstr &MI) const;
- std::string getSchedInfoStr(MCInst const &MCI) const override;
-
/// This is called after a .mir file was loaded.
virtual void mirFileLoaded(MachineFunction &MF) const;
};