Update prebuilt Clang to match Android kernel.
Bug: 132428451
Change-Id: I8f6e2cb23f381fc0c02ddea99b867e58e925e5be
diff --git a/linux-x64/clang/include/llvm/CodeGen/MachineInstr.h b/linux-x64/clang/include/llvm/CodeGen/MachineInstr.h
index 7c4e771..4cb39c5 100644
--- a/linux-x64/clang/include/llvm/CodeGen/MachineInstr.h
+++ b/linux-x64/clang/include/llvm/CodeGen/MachineInstr.h
@@ -1,9 +1,8 @@
//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -408,7 +407,7 @@
/// Returns the opcode of this MachineInstr.
unsigned getOpcode() const { return MCID->Opcode; }
- /// Access to explicit operands of the instruction.
+ /// Retuns the total number of operands.
unsigned getNumOperands() const { return NumOperands; }
const MachineOperand& getOperand(unsigned i) const {
@@ -1012,10 +1011,13 @@
}
bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
- bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
+ bool isInlineAsm() const {
+ return getOpcode() == TargetOpcode::INLINEASM ||
+ getOpcode() == TargetOpcode::INLINEASM_BR;
+ }
bool isMSInlineAsm() const {
- return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
+ return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
}
bool isStackAligningInlineAsm() const;
@@ -1400,6 +1402,19 @@
/// Return true if all the defs of this instruction are dead.
bool allDefsAreDead() const;
+ /// Return a valid size if the instruction is a spill instruction.
+ Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
+
+ /// Return a valid size if the instruction is a folded spill instruction.
+ Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
+
+ /// Return a valid size if the instruction is a restore instruction.
+ Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
+
+ /// Return a valid size if the instruction is a folded restore instruction.
+ Optional<unsigned>
+ getFoldedRestoreSize(const TargetInstrInfo *TII) const;
+
/// Copy implicit register operands from specified
/// instruction to this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
@@ -1526,6 +1541,8 @@
/// not modify the MIFlags of this MachineInstr.
uint16_t mergeFlagsWith(const MachineInstr& Other) const;
+ static uint16_t copyFlagsFromInstruction(const Instruction &I);
+
/// Copy all flags to MachineInst MIFlags
void copyIRFlags(const Instruction &I);