| Fuad Tabba | f1d6dc5 | 2019-09-18 17:33:14 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2019 The Hafnium Authors. |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * https://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #pragma once |
| 18 | |
| 19 | #include "hf/arch/types.h" |
| 20 | |
| 21 | #include "hf/cpu.h" |
| 22 | |
| 23 | #include "vmapi/hf/spci.h" |
| 24 | |
| 25 | /** |
| 26 | * PMCR_EL0.N: Indicates the number of event counters implemented. |
| 27 | */ |
| 28 | #define PMCR_EL0_N_MASK 0xf800 |
| 29 | #define PMCR_EL0_N_SHIFT 11 |
| 30 | #define GET_PMCR_EL0_N(pmcr) ((PMCR_EL0_N_MASK & (pmcr)) >> PMCR_EL0_N_SHIFT) |
| 31 | |
| 32 | /** |
| 33 | * Set to disable cycle counting when event counting is prohibited. |
| 34 | */ |
| 35 | #define PMCR_EL0_DP 0x10 |
| 36 | |
| 37 | /** |
| 38 | * Set to enable export of events where not prohibited. |
| 39 | */ |
| 40 | #define PMCR_EL0_X 0x8 |
| 41 | |
| 42 | /** |
| 43 | * Set to enable event counting. |
| 44 | */ |
| 45 | #define PMCR_EL0_E 0x1 |
| 46 | |
| 47 | /** |
| 48 | * Set to disable cycle counting in EL1. |
| 49 | */ |
| 50 | #define PMCCFILTR_EL0_P 0x80000000 |
| 51 | |
| 52 | /** |
| 53 | * Set to disable cycle counting in EL0. |
| 54 | */ |
| 55 | #define PMCCFILTR_EL0_U 0x40000000 |
| 56 | |
| 57 | /** |
| 58 | * Cycle counting in non-secure EL1 is enabled if NSK == P. |
| 59 | */ |
| 60 | #define PMCCFILTR_EL0_NSK 0x20000000 |
| 61 | |
| 62 | /** |
| 63 | * Cycle counting in non-secure EL0 is enabled if NSU == U. |
| 64 | */ |
| 65 | #define PMCCFILTR_EL0_NSU 0x10000000 |
| 66 | |
| 67 | /** |
| 68 | * Set to enable cycle counting in EL2. |
| 69 | */ |
| 70 | #define PMCCFILTR_EL0_NSH 0x8000000 |
| 71 | |
| 72 | /** |
| 73 | * Cycle counting in EL3 is enabled if M == P. |
| 74 | */ |
| 75 | #define PMCCFILTR_EL0_M 0x4000000 |
| 76 | |
| 77 | /** |
| 78 | * Cycle counting in Secutre EL2 is enabled if SH != NSH. |
| 79 | */ |
| 80 | #define PMCCFILTR_EL0_SH 0x1000000 |
| 81 | |
| 82 | bool perfmon_is_register_access(uintreg_t esr_el2); |
| 83 | |
| 84 | bool perfmon_process_access(struct vcpu *vcpu, spci_vm_id_t vm_id, |
| 85 | uintreg_t esr_el2); |
| 86 | |
| 87 | uintreg_t perfmon_get_pmccfiltr_el0_init_value(spci_vm_id_t vm_id); |