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Andrew Scull11a4a0c2018-12-29 11:38:31 +00001/*
Andrew Walbran692b3252019-03-07 15:51:31 +00002 * Copyright 2018 The Hafnium Authors.
Andrew Scull11a4a0c2018-12-29 11:38:31 +00003 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * https://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Andrew Scull9a6384b2019-01-02 12:08:40 +000017#include "hf/arch/cpu.h"
Andrew Scull11a4a0c2018-12-29 11:38:31 +000018
Andrew Walbrand4d2fa12019-10-01 16:47:25 +010019#include "hf/spci.h"
20
Andrew Scull11a4a0c2018-12-29 11:38:31 +000021void arch_irq_disable(void)
22{
23 /* TODO */
24}
25
26void arch_irq_enable(void)
27{
28 /* TODO */
29}
30
Andrew Walbran95534922019-06-19 11:32:54 +010031void arch_regs_reset(struct arch_regs *r, bool is_primary, spci_vm_id_t vm_id,
Andrew Walbran4d3fa282019-06-26 13:31:15 +010032 cpu_id_t vcpu_id, paddr_t table)
Andrew Scull11a4a0c2018-12-29 11:38:31 +000033{
34 /* TODO */
35 (void)is_primary;
Andrew Scullbb3ab6c2018-11-26 20:38:49 +000036 (void)vm_id;
Andrew Scull11a4a0c2018-12-29 11:38:31 +000037 (void)table;
Andrew Scullbb3ab6c2018-11-26 20:38:49 +000038 r->vcpu_id = vcpu_id;
Andrew Scull11a4a0c2018-12-29 11:38:31 +000039}
40
41void arch_regs_set_pc_arg(struct arch_regs *r, ipaddr_t pc, uintreg_t arg)
42{
43 (void)pc;
44 r->r[0] = arg;
45}
46
Andrew Walbrand4d2fa12019-10-01 16:47:25 +010047void arch_regs_set_retval(struct arch_regs *r, struct spci_value v)
Andrew Scull11a4a0c2018-12-29 11:38:31 +000048{
Andrew Walbrand4d2fa12019-10-01 16:47:25 +010049 r->r[0] = v.func;
50 r->r[1] = v.arg1;
51 r->r[2] = v.arg2;
52 r->r[3] = v.arg3;
53 r->r[4] = v.arg4;
54 r->r[5] = v.arg5;
55 r->r[6] = v.arg6;
56 r->r[7] = v.arg7;
Andrew Scull11a4a0c2018-12-29 11:38:31 +000057}