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Andrew Scull11a4a0c2018-12-29 11:38:31 +00001/*
Andrew Walbran692b3252019-03-07 15:51:31 +00002 * Copyright 2018 The Hafnium Authors.
Andrew Scull11a4a0c2018-12-29 11:38:31 +00003 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * https://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Andrew Scull9a6384b2019-01-02 12:08:40 +000017#include "hf/arch/cpu.h"
18
Andrew Scull11a4a0c2018-12-29 11:38:31 +000019#include <stdbool.h>
20#include <stddef.h>
21#include <stdint.h>
22
23#include "hf/addr.h"
Andrew Scull8d9e1212019-04-05 13:52:55 +010024#include "hf/std.h"
Andrew Scull11a4a0c2018-12-29 11:38:31 +000025
26void arch_irq_disable(void)
27{
28 __asm__ volatile("msr DAIFSet, #0xf");
29}
30
31void arch_irq_enable(void)
32{
33 __asm__ volatile("msr DAIFClr, #0xf");
34}
35
Andrew Scullbb3ab6c2018-11-26 20:38:49 +000036void arch_regs_reset(struct arch_regs *r, bool is_primary, uint64_t vm_id,
37 uint64_t vcpu_id, paddr_t table)
Andrew Scull11a4a0c2018-12-29 11:38:31 +000038{
Andrew Scullc960c032018-10-24 15:13:35 +010039 uintreg_t pc = r->pc;
40 uintreg_t arg = r->r[0];
Andrew Scull11a4a0c2018-12-29 11:38:31 +000041 uintreg_t hcr;
42 uintreg_t cptr;
43 uintreg_t cnthctl;
44
Andrew Scull2b5fbad2019-04-05 13:55:56 +010045 memset_s(r, sizeof(*r), 0, sizeof(*r));
Andrew Scullc960c032018-10-24 15:13:35 +010046
47 r->pc = pc;
48 r->r[0] = arg;
49
Andrew Scull11a4a0c2018-12-29 11:38:31 +000050 /* TODO: Determine if we need to set TSW. */
51 hcr = (1u << 31) | /* RW bit. */
52 (1u << 21) | /* TACR, trap access to ACTRL_EL1. */
53 (1u << 19) | /* TSC, trap SMC instructions. */
54 (1u << 20) | /* TIDCP, trap impl-defined funct. */
55 (1u << 2) | /* PTW, Protected Table Walk. */
56 (1u << 0); /* VM: enable stage-2 translation. */
57
58 cptr = 0;
59 cnthctl = 0;
60
61 if (is_primary) {
62 cnthctl |=
63 (1u << 0) | /* EL1PCTEN, don't trap phys cnt access. */
64 (1u << 1); /* EL1PCEN, don't trap phys timer access. */
65 } else {
66 hcr |= (7u << 3) | /* AMO, IMO, FMO bits. */
67 (1u << 9) | /* FB bit. */
68 (1u << 10) | /* BSU bits set to inner-sh. */
69 (3u << 13); /* TWI, TWE bits. */
70
71 cptr |= (1u << 10); /* TFP, trap fp access. */
72 }
73
74 r->lazy.hcr_el2 = hcr;
75 r->lazy.cptr_el2 = cptr;
76 r->lazy.cnthctl_el2 = cnthctl;
Andrew Scullbb3ab6c2018-11-26 20:38:49 +000077 r->lazy.vttbr_el2 = pa_addr(table) | (vm_id << 48);
78 r->lazy.vmpidr_el2 = vcpu_id;
Andrew Scull11a4a0c2018-12-29 11:38:31 +000079 /* TODO: Use constant here. */
80 r->spsr = 5 | /* M bits, set to EL1h. */
81 (0xf << 6); /* DAIF bits set; disable interrupts. */
82}
83
84void arch_regs_set_pc_arg(struct arch_regs *r, ipaddr_t pc, uintreg_t arg)
85{
86 r->pc = ipa_addr(pc);
87 r->r[0] = arg;
88}
89
90void arch_regs_set_retval(struct arch_regs *r, uintreg_t v)
91{
92 r->r[0] = v;
93}