Change log for the v2.5 TF-A release
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Ia371827ced8511b4df84cc4da60c093ff657a9a0
diff --git a/docs/ChangeLog.md b/docs/ChangeLog.md
index 48d5c15..23755e3 100644
--- a/docs/ChangeLog.md
+++ b/docs/ChangeLog.md
@@ -1,4 +1,86 @@
-# Change log
+# Change log
+
+## v2.5
+#### Highlights
+* BTI/Pointer authentication support
+ * Add branch protection build option for FEAT_PAuth and FEAT_BTI to the
+ clang command line. This only affects the S-EL2 image.
+ * Enable pointer authentication by supplying a platform defined pseudo
+ random key.
+ * Enable BTI by setting the guarded page bit in MMU descriptors for
+ executable pages.
+* SMMUv3.2 S-EL2 support
+ * Add support for SMMUv3 driver to perform stage 2 translation, protection
+ and isolation of upstream peripheral device's DMA transactions.
+* FF-A v1.0 Non-secure interrupt handling
+ * Trap physical interrupts to S-EL2 when running a SP.
+ * Handle non secure interrupts that occur while an SP is executing,
+ performing managed exit if supported.
+ * Add basic support for the GICv3 interrupt controller for the AArch64
+ platform.
+* FF-A power management support at boot time
+ * Provide platform-independent power management implementations for the
+ Hypervisor and SPMC.
+ * Implement the FFA_SECONDARY_EP_REGISTER interface for an MP SP or SPMC
+ to register the secondary core cold boot entry point for each of their
+ execution contexts.
+ * Introduce a generic "SPMD handler" to process the power management events
+ that may be conveyed from SPMD to SPMC, such as core off.
+* FF-A Direct message interfaces
+ * Introduce SP to SP direct messaging.
+ * Fix bug in the MP SP to UP SP direct response handling.
+* FF-A Memory sharing interfaces
+ * Introduce SP to SP memory sharing.
+ * When a sender of a memory management operation reclaims memory, set the
+ memory regions permissions back to it's original configuration.
+ * Require default permissions to be supplied to the function
+ 'ffa_memory_permissions_to_mode', so in the case where no permissions are
+ specified for a memory operation, the data and instruction permissions can
+ be set to the default.
+ * Encode Bit[63] of the memory region handle according to if the handle is
+ allocated by the Hypervisor or SPMC.
+* FF-A v1.0 spec compliance
+ * Return INVALID_PARAMETER error code instead of NOT_SUPPORTED for direct
+ messaging interfaces when an invalid sender or receiver id is given.
+ * Check that reserved parameter registers are 0 when invoking direct
+ messaging ABI interfaces.
+ * For SMC32 compliant direct message interfaces, only copy 32-bits
+ parameter values.
+ * Change the FF-A error codes to 32-bit to match the FF-A specification.
+ * Fix consistency with maintaining the calling convention bit of the
+ func id between the ffa_handler and the FFA_FEATURES function.
+* Remove primary VM dependencies in the SPMC
+ * Treat normal world as primary VM when running in the secure world.
+ * Create an SPMC boot flow.
+* Hafnium CI
+ * Enable Hafnium CI to include tests for Hafnium SPMC.
+ * Add basic exception handler to service VM's.
+* SIMD support
+ * Add saving/restoring of other world FP/NEON/SIMD state when entering and
+ exiting the SPMC.
+* SPMC early boot cache fix
+ * Import data cache clean and invalidation helpers from TF-A project and
+ provide an arch module for cache operations.
+ * Invalidate the SPMC image in the data cache at boot time to prevent
+ potential access to stale cache entries left by earlier boots stages.
+* Misc and bug fixes
+ * Complete vCPU state save prior to normal world exit.
+ * Update S-EL2 Stage-1 page table shareability from outer to inner.
+ * Add PL011 UART initialization code to set the IDRD and FBRD registers
+ according to the UART clock and baud rate specified at build time.
+ * License script checker fixes.
+
+#### Known limitations:
+* Secure interrupts not supported.
+* FF-A indirect message interface not supported in the secure world.
+* Only supporting models of MultiProcessor SP (vCPUs pinned to physical
+ CPUs) or UniProcessor SP (single vCPU).
+* The first secure partition booted must be a MP SP.
+* FFA_RXTX_UNMAP not implemented.
+* Use of an alternate caller provided buffer from RX/TX buffers for memory
+ sharing operations is not implemented.
+* A memory retrieve request to SPMC does not support the caller endpoint to
+ provide the range of IPA addresses to map the region to.
## v2.4
@@ -8,6 +90,7 @@
The normal world Hypervisor is maintained functional along with the
Hafnium CI test suite.
+#### Highlights
* FF-A v1.0 Setup and discovery interface
* Hypervisor implementation re-used and extended to the SPMC and SPs.
* Added partition info get ABI and appropriate properties response depending
@@ -56,15 +139,15 @@
* Removed legacy Hypervisor calls.
* Fix CPTR_EL2 TTA bit position.
* Report FAR_EL2 on injecting EL1 exception.
-* Known limitations:
- * Not all fields of the FF-A manifest are actually processed by the Hafnium
- device-tree parser.
- * SP to SP communication not supported.
- * SP to SP memory sharing not supported.
- * S-EL1 and SIMD contexts shall be saved/restored by EL3.
- * Multi-endpoint memory sharing not supported.
- * Interrupt management limited to trapping physical interrupts to
- the first S-EL1 SP. Physical interrupt trapping at S-EL2 planned as
- next release improvement.
- * Validation mostly performed using first SP Execution Context (vCPU0). More
- comprehensive multicore enablement planned as next release improvement.
+#### Known limitations:
+* Not all fields of the FF-A manifest are actually processed by the Hafnium
+ device-tree parser.
+* SP to SP communication not supported.
+* SP to SP memory sharing not supported.
+* S-EL1 and SIMD contexts shall be saved/restored by EL3.
+* Multi-endpoint memory sharing not supported.
+* Interrupt management limited to trapping physical interrupts to
+ the first S-EL1 SP. Physical interrupt trapping at S-EL2 planned as
+ next release improvement.
+* Validation mostly performed using first SP Execution Context (vCPU0). More
+ comprehensive multicore enablement planned as next release improvement.