Switch to fully flushing the data cache.

PSCI says the caches should be clean and invalidated at the entry point
so that is what we should do. Shared memory should also be flushed to
reduce the chance of coherency issues in the VMs.

Change-Id: I99c1f1fa7b44d290dc81e7d5496f4f90192c08c5
diff --git a/test/hftest/power_mgmt.c b/test/hftest/power_mgmt.c
index 576c6bd..2daba31 100644
--- a/test/hftest/power_mgmt.c
+++ b/test/hftest/power_mgmt.c
@@ -67,10 +67,12 @@
 	s_arch.arg = (uintptr_t)&s;
 
 	/*
-	 * Write back the `cpu_start_state` struct because the new CPU will be
+	 * Flush the `cpu_start_state` struct because the new CPU will be
 	 * started without caching enabled and will need the data early on.
+	 * Write back is all that is really needed so flushing will definitely
+	 * get the job done.
 	 */
-	arch_mm_write_back_dcache(&s_arch, sizeof(s_arch));
+	arch_mm_flush_dcache(&s_arch, sizeof(s_arch));
 
 	if ((s_arch.initial_sp % STACK_ALIGN) != 0) {
 		HFTEST_FAIL(true,