Switch to fully flushing the data cache.
PSCI says the caches should be clean and invalidated at the entry point
so that is what we should do. Shared memory should also be flushed to
reduce the chance of coherency issues in the VMs.
Change-Id: I99c1f1fa7b44d290dc81e7d5496f4f90192c08c5
diff --git a/inc/hf/arch/mm.h b/inc/hf/arch/mm.h
index 7156e4d..d470d08 100644
--- a/inc/hf/arch/mm.h
+++ b/inc/hf/arch/mm.h
@@ -112,10 +112,11 @@
void arch_mm_invalidate_stage2_range(ipaddr_t va_begin, ipaddr_t va_end);
/**
- * Writes the given range of virtual memory back to the point of unification so
- * all cores and devices will see the updated values.
+ * Writes back the given range of virtual memory to such a point that all cores
+ * and devices will see the updated values. The corresponding cache lines are
+ * also invalidated.
*/
-void arch_mm_write_back_dcache(void *base, size_t size);
+void arch_mm_flush_dcache(void *base, size_t size);
/**
* Gets the maximum level allowed in the page table for stage-1.