VHE: Add asid/vmid to the arch TLB invalidation APIs
Extended the TLB invalidation APIs to take asid/vmid depending on
whether it is stage1/stage2.
Change-Id: I47435028d3e34320d8e74519a6caa17d5f28c40f
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
diff --git a/inc/hf/arch/mm.h b/inc/hf/arch/mm.h
index 3c4e27a..714a6d5 100644
--- a/inc/hf/arch/mm.h
+++ b/inc/hf/arch/mm.h
@@ -98,12 +98,14 @@
/**
* Invalidates the given range of stage-1 TLB.
*/
-void arch_mm_invalidate_stage1_range(vaddr_t va_begin, vaddr_t va_end);
+void arch_mm_invalidate_stage1_range(uint16_t asid, vaddr_t va_begin,
+ vaddr_t va_end);
/**
* Invalidates the given range of stage-2 TLB.
*/
-void arch_mm_invalidate_stage2_range(ipaddr_t va_begin, ipaddr_t va_end);
+void arch_mm_invalidate_stage2_range(uint16_t vmid, ipaddr_t va_begin,
+ ipaddr_t va_end);
/**
* Writes back the given range of virtual memory to such a point that all cores