Fixing checkpatch.pl warnings.
Most warnings are "Missing a blank line after declarations". I'm also
adding blank lines between multi-line comments and statements.
Ran with --ignore BRACES,SPDX_LICENSE_TAG,VOLATILE,SPLIT_STRING,
AVOID_EXTERNS,USE_SPINLOCK_T,NEW_TYPEDEFS,INITIALISED_STATIC,
FILE_PATH_CHANGES to reduce noise. Now there is only one type of
warning, with two instances:
WARNING: Prefer using '"%s...", __func__' to using 'dmb', this function's name, in a string
+ __asm__ volatile("dmb sy");
WARNING: Prefer using '"%s...", __func__' to using 'dsb', this function's name, in a string
+ __asm__ volatile("dsb sy");
Change-Id: Id837feef86dc81ba84de1809e76653ddce814422
diff --git a/src/arch/aarch64/handler.c b/src/arch/aarch64/handler.c
index 2f84a90..d341580 100644
--- a/src/arch/aarch64/handler.c
+++ b/src/arch/aarch64/handler.c
@@ -89,18 +89,14 @@
}
dlog("\n");
- for (;;) {
- /* do nothing */
- }
+ break;
default:
dlog("Unknown current sync exception pc=0x%x, esr=0x%x, "
"ec=0x%x\n",
elr, esr, esr >> 26);
- for (;;) {
- /* do nothing */
- }
}
+
for (;;) {
/* do nothing */
}
@@ -227,6 +223,7 @@
static void set_virtual_interrupt_current(bool enable)
{
uintreg_t hcr_el2 = read_msr(hcr_el2);
+
if (enable) {
hcr_el2 |= HCR_EL2_VI;
} else {
@@ -244,6 +241,7 @@
if (current()->vm->id == HF_PRIMARY_VM_ID) {
int32_t psci_ret;
+
if (psci_handler(arg0, arg1, arg2, arg3, &psci_ret)) {
ret.user_ret = psci_ret;
return ret;
@@ -382,6 +380,7 @@
for (;;) {
/* do nothing */
}
+ break;
case 0x20: /* EC = 100000, Instruction abort. */
dlog("Lower instruction abort: pc=0x%x, esr=0x%x, ec=0x%x, "
@@ -400,6 +399,7 @@
for (;;) {
/* do nothing */
}
+ break;
case 0x17: /* EC = 010111, SMC instruction. */
if (vcpu->vm->id != HF_PRIMARY_VM_ID ||
diff --git a/src/arch/aarch64/hftest/interrupts_gicv3.c b/src/arch/aarch64/hftest/interrupts_gicv3.c
index 01d331d..d99df0c 100644
--- a/src/arch/aarch64/hftest/interrupts_gicv3.c
+++ b/src/arch/aarch64/hftest/interrupts_gicv3.c
@@ -27,7 +27,7 @@
extern uint8_t vector_table_el1;
-void exception_setup()
+void exception_setup(void)
{
/* Set exception vector table. */
write_msr(VBAR_EL1, &vector_table_el1);
@@ -35,7 +35,7 @@
write_msr(ICC_CTLR_EL1, 0);
}
-void interrupt_gic_setup()
+void interrupt_gic_setup(void)
{
GICD_CTLR = 1u << 4 /* Enable affinity routing. */
| 1u << 1; /* Enable group 1 non-secure interrupts. */
@@ -75,6 +75,7 @@
void interrupt_enable_all(bool enable)
{
uint32_t i;
+
if (enable) {
GICR_ISENABLER0 = 0xffffffff;
for (i = 0; i < 32; ++i) {
@@ -101,6 +102,7 @@
void interrupt_set_edge_triggered(uint32_t intid, bool edge_triggered)
{
uint32_t bit = 1u << (intid % 16 * 2 + 1);
+
if (intid < 32) {
if (edge_triggered) {
GICR_ICFGR(intid / 16) |= bit;
@@ -124,10 +126,11 @@
((uint64_t)target_list) | ((uint64_t)affinity1 << 16) |
(((uint64_t)intid & 0x0f) << 24) | ((uint64_t)affinity2 << 32) |
((uint64_t)irm << 40) | ((uint64_t)affinity3 << 48);
+
write_msr(ICC_SGI1R_EL1, sgi_register);
}
-uint32_t interrupt_get_and_acknowledge()
+uint32_t interrupt_get_and_acknowledge(void)
{
return read_msr(ICC_IAR1_EL1);
}
@@ -150,18 +153,14 @@
}
dlog("\n");
- for (;;) {
- /* do nothing */
- }
+ break;
default:
dlog("Unknown current sync exception pc=0x%x, esr=0x%x, "
"ec=0x%x\n",
elr, esr, esr >> 26);
- for (;;) {
- /* do nothing */
- }
}
+
for (;;) {
/* do nothing */
}
diff --git a/src/arch/aarch64/hftest/power_mgmt.c b/src/arch/aarch64/hftest/power_mgmt.c
index 05f4061..a1c1801 100644
--- a/src/arch/aarch64/hftest/power_mgmt.c
+++ b/src/arch/aarch64/hftest/power_mgmt.c
@@ -44,6 +44,7 @@
void vm_cpu_entry(struct cpu_start_state *s)
{
struct cpu_start_state local = *(volatile struct cpu_start_state *)s;
+
sl_unlock(&s->lock);
local.entry(local.arg);
@@ -59,8 +60,8 @@
bool cpu_start(uintptr_t id, void *stack, size_t stack_size,
void (*entry)(uintptr_t arg), uintptr_t arg)
{
- struct cpu_start_state s;
void vm_cpu_entry_raw(uintptr_t arg);
+ struct cpu_start_state s;
/* Initialise the temporary state we'll hold on the stack. */
sl_init(&s.lock);
diff --git a/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h b/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h
index a581964..9083103 100644
--- a/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h
+++ b/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h
@@ -44,8 +44,8 @@
#define GICR_ISACTIVER0 (*(volatile uint32_t *)(SGI_BASE + 0x0300))
#define GICR_ICFGR(n) (((volatile uint32_t *)(SGI_BASE + 0x0c00))[n])
-void exception_setup();
-void interrupt_gic_setup();
+void exception_setup(void);
+void interrupt_gic_setup(void);
void interrupt_enable(uint32_t intid, bool enable);
void interrupt_enable_all(bool enable);
void interrupt_set_priority_mask(uint8_t min_priority);
@@ -54,5 +54,5 @@
void interrupt_send_sgi(uint8_t intid, bool irm, uint8_t affinity3,
uint8_t affinity2, uint8_t affinity1,
uint16_t target_list);
-uint32_t interrupt_get_and_acknowledge();
+uint32_t interrupt_get_and_acknowledge(void);
void interrupt_end(uint32_t intid);
diff --git a/src/arch/aarch64/io.h b/src/arch/aarch64/io.h
index 07d410b..a355364 100644
--- a/src/arch/aarch64/io.h
+++ b/src/arch/aarch64/io.h
@@ -29,8 +29,10 @@
static inline uint32_t io_read_mb(uintptr_t addr)
{
uint32_t v = io_read(addr);
+
dsb();
isb();
+
return v;
}
diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
index 168ce24..98eb251 100644
--- a/src/arch/aarch64/mm.c
+++ b/src/arch/aarch64/mm.c
@@ -128,6 +128,7 @@
pte_t arch_mm_block_pte(uint8_t level, paddr_t pa, uint64_t attrs)
{
pte_t pte = pa_addr(pa) | attrs;
+
if (level == 0) {
/* A level 0 'block' is actually a page entry. */
pte |= PTE_LEVEL0_BLOCK;
@@ -287,10 +288,12 @@
uint16_t line_size = 1 << ((read_msr(CTR_EL0) >> 16) & 0xf);
uintptr_t line_begin = (uintptr_t)base & ~(line_size - 1);
uintptr_t end = (uintptr_t)base + size;
+
while (line_begin < end) {
__asm__ volatile("dc cvac, %0" : : "r"(line_begin));
line_begin += line_size;
}
+
__asm__ volatile("dsb sy");
}
diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h
index d55a110..3989342 100644
--- a/src/arch/aarch64/msr.h
+++ b/src/arch/aarch64/msr.h
@@ -27,9 +27,5 @@
__v; \
})
-#define write_msr(name, value) \
- do { \
- __asm__ volatile("msr " #name ", %x0" \
- : \
- : "rZ"((uintreg_t)(value))); \
- } while (0)
+#define write_msr(name, value) \
+ __asm__ volatile("msr " #name ", %x0" : : "rZ"((uintreg_t)(value)))