Fixing checkpatch.pl warnings.
Most warnings are "Missing a blank line after declarations". I'm also
adding blank lines between multi-line comments and statements.
Ran with --ignore BRACES,SPDX_LICENSE_TAG,VOLATILE,SPLIT_STRING,
AVOID_EXTERNS,USE_SPINLOCK_T,NEW_TYPEDEFS,INITIALISED_STATIC,
FILE_PATH_CHANGES to reduce noise. Now there is only one type of
warning, with two instances:
WARNING: Prefer using '"%s...", __func__' to using 'dmb', this function's name, in a string
+ __asm__ volatile("dmb sy");
WARNING: Prefer using '"%s...", __func__' to using 'dsb', this function's name, in a string
+ __asm__ volatile("dsb sy");
Change-Id: Id837feef86dc81ba84de1809e76653ddce814422
diff --git a/src/api.c b/src/api.c
index e122107..d8df3e4 100644
--- a/src/api.c
+++ b/src/api.c
@@ -41,8 +41,8 @@
static struct mpool api_page_pool;
/**
- * Initialies the API page pool by taking ownership of the contents of the given
- * page pool.
+ * Initialises the API page pool by taking ownership of the contents of the
+ * given page pool.
*/
void api_init(struct mpool *ppool)
{
@@ -84,6 +84,7 @@
struct hf_vcpu_run_return ret = {
.code = HF_VCPU_RUN_YIELD,
};
+
return api_switch_to_primary(current, ret, vcpu_state_ready);
}
@@ -96,6 +97,7 @@
struct hf_vcpu_run_return ret = {
.code = HF_VCPU_RUN_WAIT_FOR_INTERRUPT,
};
+
return api_switch_to_primary(current, ret,
vcpu_state_blocked_interrupt);
}
@@ -174,8 +176,8 @@
/*
* Wait until the registers become available. Care must be taken when
- * looping on this: it shouldn't be done while holding other locks
- * to avoid deadlocks.
+ * looping on this: it shouldn't be done while holding other locks to
+ * avoid deadlocks.
*/
while (!vcpu->regs_available) {
sl_unlock(&vcpu->lock);
@@ -395,6 +397,7 @@
.code = HF_VCPU_RUN_MESSAGE,
.message.size = size,
};
+
*next = api_switch_to_primary(current, primary_ret,
vcpu_state_ready);
ret = 0;
@@ -445,6 +448,7 @@
.wake_up.vm_id = to->id,
.wake_up.vcpu = vcpu,
};
+
*next = api_switch_to_primary(current, primary_ret,
vcpu_state_ready);
ret = 0;
@@ -506,6 +510,7 @@
struct hf_vcpu_run_return run_return = {
.code = HF_VCPU_RUN_WAIT_FOR_INTERRUPT,
};
+
*next = api_switch_to_primary(current, run_return,
vcpu_state_blocked_mailbox);
}
@@ -550,6 +555,7 @@
{
uint32_t intid_index = intid / INTERRUPT_REGISTER_BITS;
uint32_t intid_mask = 1u << (intid % INTERRUPT_REGISTER_BITS);
+
if (intid >= HF_NUM_INTIDS) {
return -1;
}
@@ -603,6 +609,7 @@
uint32_t enabled_and_pending =
current->interrupts.interrupt_enabled[i] &
current->interrupts.interrupt_pending[i];
+
if (enabled_and_pending != 0) {
uint8_t bit_index = ctz(enabled_and_pending);
/*
@@ -629,6 +636,7 @@
struct vcpu *current)
{
uint32_t current_vm_id = current->vm->id;
+
/*
* The primary VM is allowed to inject interrupts into any VM. Secondary
* VMs are only allowed to inject interrupts into their own vCPUs.
@@ -664,16 +672,20 @@
if (intid >= HF_NUM_INTIDS) {
return -1;
}
+
if (target_vm == NULL) {
return -1;
}
+
if (target_vcpu_idx >= target_vm->vcpu_count) {
/* The requested vcpu must exist. */
return -1;
}
+
if (!is_injection_allowed(target_vm_id, current)) {
return -1;
}
+
target_vcpu = &target_vm->vcpus[target_vcpu_idx];
dlog("Injecting IRQ %d for VM %d VCPU %d from VM %d VCPU %d\n", intid,
@@ -754,6 +766,7 @@
previous_next_pointer =
&(*previous_next_pointer)->mailbox_next;
}
+
if (*previous_next_pointer == NULL) {
dlog("Target VCPU state is vcpu_state_blocked_mailbox "
"but is not in VM mailbox waiter list. This "
@@ -779,6 +792,7 @@
.wake_up.vm_id = target_vm_id,
.wake_up.vcpu = target_vcpu_idx,
};
+
*next = api_switch_to_primary(current, ret, vcpu_state_ready);
}
diff --git a/src/arch/aarch64/handler.c b/src/arch/aarch64/handler.c
index 2f84a90..d341580 100644
--- a/src/arch/aarch64/handler.c
+++ b/src/arch/aarch64/handler.c
@@ -89,18 +89,14 @@
}
dlog("\n");
- for (;;) {
- /* do nothing */
- }
+ break;
default:
dlog("Unknown current sync exception pc=0x%x, esr=0x%x, "
"ec=0x%x\n",
elr, esr, esr >> 26);
- for (;;) {
- /* do nothing */
- }
}
+
for (;;) {
/* do nothing */
}
@@ -227,6 +223,7 @@
static void set_virtual_interrupt_current(bool enable)
{
uintreg_t hcr_el2 = read_msr(hcr_el2);
+
if (enable) {
hcr_el2 |= HCR_EL2_VI;
} else {
@@ -244,6 +241,7 @@
if (current()->vm->id == HF_PRIMARY_VM_ID) {
int32_t psci_ret;
+
if (psci_handler(arg0, arg1, arg2, arg3, &psci_ret)) {
ret.user_ret = psci_ret;
return ret;
@@ -382,6 +380,7 @@
for (;;) {
/* do nothing */
}
+ break;
case 0x20: /* EC = 100000, Instruction abort. */
dlog("Lower instruction abort: pc=0x%x, esr=0x%x, ec=0x%x, "
@@ -400,6 +399,7 @@
for (;;) {
/* do nothing */
}
+ break;
case 0x17: /* EC = 010111, SMC instruction. */
if (vcpu->vm->id != HF_PRIMARY_VM_ID ||
diff --git a/src/arch/aarch64/hftest/interrupts_gicv3.c b/src/arch/aarch64/hftest/interrupts_gicv3.c
index 01d331d..d99df0c 100644
--- a/src/arch/aarch64/hftest/interrupts_gicv3.c
+++ b/src/arch/aarch64/hftest/interrupts_gicv3.c
@@ -27,7 +27,7 @@
extern uint8_t vector_table_el1;
-void exception_setup()
+void exception_setup(void)
{
/* Set exception vector table. */
write_msr(VBAR_EL1, &vector_table_el1);
@@ -35,7 +35,7 @@
write_msr(ICC_CTLR_EL1, 0);
}
-void interrupt_gic_setup()
+void interrupt_gic_setup(void)
{
GICD_CTLR = 1u << 4 /* Enable affinity routing. */
| 1u << 1; /* Enable group 1 non-secure interrupts. */
@@ -75,6 +75,7 @@
void interrupt_enable_all(bool enable)
{
uint32_t i;
+
if (enable) {
GICR_ISENABLER0 = 0xffffffff;
for (i = 0; i < 32; ++i) {
@@ -101,6 +102,7 @@
void interrupt_set_edge_triggered(uint32_t intid, bool edge_triggered)
{
uint32_t bit = 1u << (intid % 16 * 2 + 1);
+
if (intid < 32) {
if (edge_triggered) {
GICR_ICFGR(intid / 16) |= bit;
@@ -124,10 +126,11 @@
((uint64_t)target_list) | ((uint64_t)affinity1 << 16) |
(((uint64_t)intid & 0x0f) << 24) | ((uint64_t)affinity2 << 32) |
((uint64_t)irm << 40) | ((uint64_t)affinity3 << 48);
+
write_msr(ICC_SGI1R_EL1, sgi_register);
}
-uint32_t interrupt_get_and_acknowledge()
+uint32_t interrupt_get_and_acknowledge(void)
{
return read_msr(ICC_IAR1_EL1);
}
@@ -150,18 +153,14 @@
}
dlog("\n");
- for (;;) {
- /* do nothing */
- }
+ break;
default:
dlog("Unknown current sync exception pc=0x%x, esr=0x%x, "
"ec=0x%x\n",
elr, esr, esr >> 26);
- for (;;) {
- /* do nothing */
- }
}
+
for (;;) {
/* do nothing */
}
diff --git a/src/arch/aarch64/hftest/power_mgmt.c b/src/arch/aarch64/hftest/power_mgmt.c
index 05f4061..a1c1801 100644
--- a/src/arch/aarch64/hftest/power_mgmt.c
+++ b/src/arch/aarch64/hftest/power_mgmt.c
@@ -44,6 +44,7 @@
void vm_cpu_entry(struct cpu_start_state *s)
{
struct cpu_start_state local = *(volatile struct cpu_start_state *)s;
+
sl_unlock(&s->lock);
local.entry(local.arg);
@@ -59,8 +60,8 @@
bool cpu_start(uintptr_t id, void *stack, size_t stack_size,
void (*entry)(uintptr_t arg), uintptr_t arg)
{
- struct cpu_start_state s;
void vm_cpu_entry_raw(uintptr_t arg);
+ struct cpu_start_state s;
/* Initialise the temporary state we'll hold on the stack. */
sl_init(&s.lock);
diff --git a/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h b/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h
index a581964..9083103 100644
--- a/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h
+++ b/src/arch/aarch64/inc/hf/arch/vm/interrupts_gicv3.h
@@ -44,8 +44,8 @@
#define GICR_ISACTIVER0 (*(volatile uint32_t *)(SGI_BASE + 0x0300))
#define GICR_ICFGR(n) (((volatile uint32_t *)(SGI_BASE + 0x0c00))[n])
-void exception_setup();
-void interrupt_gic_setup();
+void exception_setup(void);
+void interrupt_gic_setup(void);
void interrupt_enable(uint32_t intid, bool enable);
void interrupt_enable_all(bool enable);
void interrupt_set_priority_mask(uint8_t min_priority);
@@ -54,5 +54,5 @@
void interrupt_send_sgi(uint8_t intid, bool irm, uint8_t affinity3,
uint8_t affinity2, uint8_t affinity1,
uint16_t target_list);
-uint32_t interrupt_get_and_acknowledge();
+uint32_t interrupt_get_and_acknowledge(void);
void interrupt_end(uint32_t intid);
diff --git a/src/arch/aarch64/io.h b/src/arch/aarch64/io.h
index 07d410b..a355364 100644
--- a/src/arch/aarch64/io.h
+++ b/src/arch/aarch64/io.h
@@ -29,8 +29,10 @@
static inline uint32_t io_read_mb(uintptr_t addr)
{
uint32_t v = io_read(addr);
+
dsb();
isb();
+
return v;
}
diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
index 168ce24..98eb251 100644
--- a/src/arch/aarch64/mm.c
+++ b/src/arch/aarch64/mm.c
@@ -128,6 +128,7 @@
pte_t arch_mm_block_pte(uint8_t level, paddr_t pa, uint64_t attrs)
{
pte_t pte = pa_addr(pa) | attrs;
+
if (level == 0) {
/* A level 0 'block' is actually a page entry. */
pte |= PTE_LEVEL0_BLOCK;
@@ -287,10 +288,12 @@
uint16_t line_size = 1 << ((read_msr(CTR_EL0) >> 16) & 0xf);
uintptr_t line_begin = (uintptr_t)base & ~(line_size - 1);
uintptr_t end = (uintptr_t)base + size;
+
while (line_begin < end) {
__asm__ volatile("dc cvac, %0" : : "r"(line_begin));
line_begin += line_size;
}
+
__asm__ volatile("dsb sy");
}
diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h
index d55a110..3989342 100644
--- a/src/arch/aarch64/msr.h
+++ b/src/arch/aarch64/msr.h
@@ -27,9 +27,5 @@
__v; \
})
-#define write_msr(name, value) \
- do { \
- __asm__ volatile("msr " #name ", %x0" \
- : \
- : "rZ"((uintreg_t)(value))); \
- } while (0)
+#define write_msr(name, value) \
+ __asm__ volatile("msr " #name ", %x0" : : "rZ"((uintreg_t)(value)))
diff --git a/src/cpu.c b/src/cpu.c
index 1ae6cd1..f87d78d 100644
--- a/src/cpu.c
+++ b/src/cpu.c
@@ -47,6 +47,7 @@
/* Initialize all CPUs. */
for (i = 0; i < MAX_CPUS; i++) {
struct cpu *c = &cpus[i];
+
cpu_init(c);
c->id = i; /* TODO: Initialize ID based on fdt. */
c->stack_bottom = &callstacks[i][STACK_SIZE];
@@ -96,6 +97,7 @@
if (!prev) {
struct vm *vm = vm_get(HF_PRIMARY_VM_ID);
struct vcpu *vcpu = &vm->vcpus[cpu_index(c)];
+
arch_regs_set_pc_arg(&vcpu->regs, entry, arg);
vcpu_on(vcpu);
}
diff --git a/src/dlog.c b/src/dlog.c
index 51ba6fb..322c054 100644
--- a/src/dlog.c
+++ b/src/dlog.c
@@ -222,6 +222,7 @@
/* Read minimum width from arguments. */
if (w == 0 && p[1] == '*') {
int v = va_arg(args, int);
+
if (v >= 0) {
w = v;
} else {
@@ -235,6 +236,7 @@
switch (p[1]) {
case 's': {
char *str = va_arg(args, char *);
+
print_string(str, str, w, flags, ' ');
p++;
} break;
@@ -242,6 +244,7 @@
case 'd':
case 'i': {
int v = va_arg(args, int);
+
if (v < 0) {
flags |= FLAG_NEG;
v = -v;
diff --git a/src/fdt.c b/src/fdt.c
index b0cc45b..cb7e524 100644
--- a/src/fdt.c
+++ b/src/fdt.c
@@ -354,6 +354,7 @@
depth++;
while (fdt_next_property(&t, &name, &buf, &size)) {
uint32_t i;
+
dlog("%*sproperty: \"%s\" (", 2 * depth, "",
name);
for (i = 0; i < size; i++) {
diff --git a/src/fdt_handler.c b/src/fdt_handler.c
index 311dec7..d0400a8 100644
--- a/src/fdt_handler.c
+++ b/src/fdt_handler.c
@@ -157,6 +157,7 @@
do {
const char *data;
uint32_t size;
+
if (!fdt_read_property(&n, "device_type", &data, &size) ||
size != sizeof("memory") ||
memcmp(data, "memory", sizeof("memory")) != 0 ||
@@ -228,6 +229,7 @@
bool fdt_unmap(struct fdt_header *fdt, struct mpool *ppool)
{
paddr_t fdt_addr = pa_from_va(va_from_ptr(fdt));
+
return mm_unmap(fdt_addr, pa_add(fdt_addr, fdt_total_size(fdt)), 0,
ppool);
}
diff --git a/src/layout.c b/src/layout.c
index 003a8ab..15dec5d 100644
--- a/src/layout.c
+++ b/src/layout.c
@@ -22,6 +22,7 @@
paddr_t layout_text_begin(void)
{
extern uint8_t text_begin[];
+
return pa_init((uintpaddr_t)text_begin);
}
@@ -31,6 +32,7 @@
paddr_t layout_text_end(void)
{
extern uint8_t text_end[];
+
return pa_init((uintpaddr_t)text_end);
}
@@ -40,6 +42,7 @@
paddr_t layout_rodata_begin(void)
{
extern uint8_t rodata_begin[];
+
return pa_init((uintpaddr_t)rodata_begin);
}
@@ -49,6 +52,7 @@
paddr_t layout_rodata_end(void)
{
extern uint8_t rodata_end[];
+
return pa_init((uintpaddr_t)rodata_end);
}
@@ -58,6 +62,7 @@
paddr_t layout_data_begin(void)
{
extern uint8_t data_begin[];
+
return pa_init((uintpaddr_t)data_begin);
}
@@ -67,6 +72,7 @@
paddr_t layout_data_end(void)
{
extern uint8_t data_end[];
+
return pa_init((uintpaddr_t)data_end);
}
@@ -76,6 +82,7 @@
paddr_t layout_initrd_begin(void)
{
extern uint8_t initrd_begin[];
+
return pa_init((uintpaddr_t)initrd_begin);
}
@@ -85,6 +92,7 @@
paddr_t layout_initrd_end(void)
{
extern uint8_t initrd_end[];
+
return pa_init((uintpaddr_t)initrd_end);
}
@@ -94,6 +102,7 @@
paddr_t layout_fdt_begin(void)
{
extern uint8_t fdt_begin[];
+
return pa_init((uintpaddr_t)fdt_begin);
}
@@ -103,6 +112,7 @@
paddr_t layout_fdt_end(void)
{
extern uint8_t fdt_end[];
+
return pa_init((uintpaddr_t)fdt_end);
}
@@ -112,6 +122,7 @@
paddr_t layout_bin_end(void)
{
extern uint8_t bin_end[];
+
return pa_init((uintpaddr_t)bin_end);
}
@@ -124,5 +135,6 @@
{
/* TODO: This is a hack. We must read the alignment from the binary. */
paddr_t bin_end = layout_bin_end();
+
return pa_init((pa_addr(bin_end) + 0x80000 - 1) & ~(0x80000 - 1));
}
diff --git a/src/load.c b/src/load.c
index 4b0880c..38159a0 100644
--- a/src/load.c
+++ b/src/load.c
@@ -177,8 +177,10 @@
{
size_t i;
- /* TODO(b/116191358): Consider being cleverer about how we pack VMs
- * together, with a non-greedy algorithm. */
+ /*
+ * TODO(b/116191358): Consider being cleverer about how we pack VMs
+ * together, with a non-greedy algorithm.
+ */
for (i = 0; i < mem_ranges_count; ++i) {
if (size_to_find <=
pa_addr(mem_ranges[i].end) - pa_addr(mem_ranges[i].begin)) {
diff --git a/src/main.c b/src/main.c
index bb19e5a..e1555cc 100644
--- a/src/main.c
+++ b/src/main.c
@@ -151,6 +151,7 @@
* by only touching the variable from cpu 0.
*/
static volatile bool inited = false;
+
if (cpu_index(c) == 0 && !inited) {
inited = true;
one_time_init();
diff --git a/src/memiter.c b/src/memiter.c
index ad98fac..8b9854c 100644
--- a/src/memiter.c
+++ b/src/memiter.c
@@ -59,9 +59,11 @@
bool memiter_iseq(const struct memiter *it, const char *str)
{
size_t len = strlen(str);
+
if (len != it->limit - it->next) {
return false;
}
+
return memcmp(it->next, str, len) == 0;
}
@@ -126,9 +128,12 @@
bool memiter_advance(struct memiter *it, size_t v)
{
const char *p = it->next + v;
+
if (p < it->next || p > it->limit) {
return false;
}
+
it->next = p;
+
return true;
}
diff --git a/src/mm.c b/src/mm.c
index 830fb289..55340a1 100644
--- a/src/mm.c
+++ b/src/mm.c
@@ -115,6 +115,7 @@
static ptable_addr_t mm_level_end(ptable_addr_t addr, uint8_t level)
{
size_t offset = PAGE_BITS + (level + 1) * PAGE_LEVEL_BITS;
+
return ((addr >> offset) + 1) << offset;
}
@@ -125,6 +126,7 @@
static size_t mm_index(ptable_addr_t addr, uint8_t level)
{
ptable_addr_t v = addr >> (PAGE_BITS + level * PAGE_LEVEL_BITS);
+
return v & ((UINT64_C(1) << PAGE_LEVEL_BITS) - 1);
}
@@ -483,6 +485,7 @@
int max_level)
{
uint64_t i;
+
for (i = 0; i < MM_PTE_PER_PAGE; i++) {
if (!arch_mm_pte_is_present(table->entries[i], level)) {
continue;
@@ -509,6 +512,7 @@
int max_level = arch_mm_max_level(mode);
uint8_t root_table_count = arch_mm_root_table_count(mode);
uint8_t i;
+
for (i = 0; i < root_table_count; ++i) {
mm_dump_table_recursive(&tables[i], max_level, max_level);
}
@@ -695,8 +699,10 @@
}
}
- /* TODO: halloc could return a virtual or physical address if mm not
- * enabled? */
+ /*
+ * TODO: halloc could return a virtual or physical address if mm not
+ * enabled?
+ */
t->root = pa_init((uintpaddr_t)tables);
return true;
diff --git a/src/mpool.c b/src/mpool.c
index 4cc1d40..6b5824e 100644
--- a/src/mpool.c
+++ b/src/mpool.c
@@ -123,6 +123,7 @@
entry = p->entry_list;
while (entry != NULL) {
void *ptr = entry;
+
entry = entry->next;
mpool_free(p->fallback, ptr);
}
@@ -132,6 +133,7 @@
while (chunk != NULL) {
void *ptr = chunk;
size_t size = (uintptr_t)chunk->limit - (uintptr_t)chunk;
+
chunk = chunk->next_chunk;
mpool_add_chunk(p->fallback, ptr, size);
}
@@ -193,6 +195,7 @@
mpool_lock(p);
if (p->entry_list != NULL) {
struct mpool_entry *entry = p->entry_list;
+
p->entry_list = entry->next;
ret = entry;
goto exit;