Enable MMU and caching in VM API tests
VM API tests are failing on real hardware because VMs are not seeing
data written by the hypervisor. The reason for this is that Hafnium has
data caching enabled while the test VMs do not. Solve this discrepancy
by enabling data caching in the VMs too, which requires enabling stage-1
MMU translation.
The entire address space is identity-mapped with read-write-execute
permisssions. Only GIC tests currently require custom device mappings.
Implementation shares ptable management code from src/mm.c and
src/arch/mm.c.
Bug: 138985026
Test: ./kokoro/ubuntu/build.sh
Change-Id: Ib9f599c448d70296a6ca869ddbb51abfcc55148d
diff --git a/src/BUILD.gn b/src/BUILD.gn
index f5108ec..8c5b6e5 100644
--- a/src/BUILD.gn
+++ b/src/BUILD.gn
@@ -17,10 +17,8 @@
# The hypervisor image.
hypervisor("hafnium") {
- sources = [
- "layout.c",
- ]
deps = [
+ ":layout",
":src_not_testable_yet",
]
}
@@ -50,8 +48,6 @@
"abort.c",
"api.c",
"cpu.c",
- "mm.c",
- "mpool.c",
"panic.c",
"spci_architected_message.c",
"vm.c",
@@ -61,6 +57,7 @@
":fdt",
":fdt_handler",
":memiter",
+ ":mm",
":std",
"//src/arch/${plat_arch}/hypervisor",
plat_console,
@@ -71,6 +68,19 @@
}
}
+source_set("layout") {
+ sources = [
+ "layout.c",
+ ]
+}
+
+source_set("mm") {
+ sources = [
+ "mm.c",
+ "mpool.c",
+ ]
+}
+
# Standard library functions.
source_set("std") {
sources = [
diff --git a/src/arch/aarch64/hftest/BUILD.gn b/src/arch/aarch64/hftest/BUILD.gn
index 4c5dace..e5bcedc 100644
--- a/src/arch/aarch64/hftest/BUILD.gn
+++ b/src/arch/aarch64/hftest/BUILD.gn
@@ -79,3 +79,9 @@
"//src/arch/aarch64/hftest:hf_call",
]
}
+
+source_set("mm") {
+ sources = [
+ "mm.c",
+ ]
+}
diff --git a/src/arch/aarch64/hftest/mm.c b/src/arch/aarch64/hftest/mm.c
new file mode 100644
index 0000000..6673d90
--- /dev/null
+++ b/src/arch/aarch64/hftest/mm.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2019 The Hafnium Authors.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "hf/mm.h"
+
+#include "hf/arch/barriers.h"
+
+#include "hf/dlog.h"
+
+#include "../msr.h"
+
+#define STAGE1_DEVICEINDX UINT64_C(0)
+#define STAGE1_NORMALINDX UINT64_C(1)
+
+/**
+ * Initialize MMU for a test running in EL1.
+ */
+bool arch_vm_mm_init(paddr_t table)
+{
+ static const int pa_bits_table[16] = {32, 36, 40, 42, 44, 48};
+ uint64_t features = read_msr(id_aa64mmfr0_el1);
+ uint64_t v;
+ int pa_bits = pa_bits_table[features & 0xf];
+
+ /* Check that 4KB granules are supported. */
+ if ((features >> 28) & 0xf) {
+ dlog("4KB granules are not supported\n");
+ return false;
+ }
+
+ /* Check the physical address range. */
+ if (!pa_bits) {
+ dlog("Unsupported value of id_aa64mmfr0_el1.PARange: %x\n",
+ features & 0xf);
+ return false;
+ }
+
+ /*
+ * 0 -> Device-nGnRnE memory
+ * 0xff -> Normal memory, Inner/Outer Write-Back Non-transient,
+ * Write-Alloc, Read-Alloc.
+ */
+ v = (0 << (8 * STAGE1_DEVICEINDX)) | (0xff << (8 * STAGE1_NORMALINDX));
+ write_msr(mair_el1, v);
+
+ write_msr(ttbr0_el1, pa_addr(table));
+
+ v = (1 << 20) | /* TBI, top byte ignored. */
+ ((features & 0xf) << 16) | /* PS. */
+ (0 << 14) | /* TG0, granule size, 4KB. */
+ (3 << 12) | /* SH0, inner shareable. */
+ (1 << 10) | /* ORGN0, normal mem, WB RA WA Cacheable. */
+ (1 << 8) | /* IRGN0, normal mem, WB RA WA Cacheable. */
+ (25 << 0) | /* T0SZ, input address is 2^39 bytes. */
+ 0;
+ write_msr(tcr_el1, v);
+
+ v = (1 << 0) | /* M, enable stage 1 EL2 MMU. */
+ (1 << 1) | /* A, enable alignment check faults. */
+ (1 << 2) | /* C, data cache enable. */
+ (1 << 3) | /* SA, enable stack alignment check. */
+ (3 << 4) | /* RES1 bits. */
+ (1 << 11) | /* RES1 bit. */
+ (1 << 12) | /* I, instruction cache enable. */
+ (1 << 16) | /* RES1 bit. */
+ (1 << 18) | /* RES1 bit. */
+ (0 << 19) | /* WXN bit, writable execute never. */
+ (3 << 22) | /* RES1 bits. */
+ (3 << 28) | /* RES1 bits. */
+ 0;
+
+ dsb(sy);
+ isb();
+ write_msr(sctlr_el1, v);
+ isb();
+
+ return true;
+}
diff --git a/src/arch/aarch64/inc/hf/arch/vm/mm.h b/src/arch/aarch64/inc/hf/arch/vm/mm.h
new file mode 100644
index 0000000..8bbb70e
--- /dev/null
+++ b/src/arch/aarch64/inc/hf/arch/vm/mm.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2019 The Hafnium Authors.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include "hf/mm.h"
+
+bool arch_vm_mm_init(paddr_t table);
diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
index 191368e..1106aa6 100644
--- a/src/arch/aarch64/mm.c
+++ b/src/arch/aarch64/mm.c
@@ -266,14 +266,22 @@
* there are too many, it is quicker to invalidate all TLB entries.
*/
if ((end - begin) > (MAX_TLBI_OPS * PAGE_SIZE)) {
- tlbi(alle2);
+ if (VM_TOOLCHAIN == 1) {
+ tlbi(vmalle1is);
+ } else {
+ tlbi(alle2);
+ }
} else {
begin >>= 12;
end >>= 12;
/* Invalidate stage-1 TLB, one page from the range at a time. */
for (it = begin; it < end;
it += (UINT64_C(1) << (PAGE_BITS - 12))) {
- tlbi_reg(vae2is, it);
+ if (VM_TOOLCHAIN == 1) {
+ tlbi_reg(vae1is, it);
+ } else {
+ tlbi_reg(vae2is, it);
+ }
}
}
diff --git a/src/mm.c b/src/mm.c
index 2a85484..995e77d 100644
--- a/src/mm.c
+++ b/src/mm.c
@@ -32,9 +32,6 @@
* contain only 1-1 mappings, aligned on the block boundaries.
*/
-/* The type of addresses stored in the page table. */
-typedef uintvaddr_t ptable_addr_t;
-
/*
* For stage 2, the input is an intermediate physical addresses rather than a
* virtual address so:
@@ -46,15 +43,6 @@
"are the same size. It looks like that assumption might not be holding "
"so we need to check that everything is going to be ok.");
-/* Keep macro alignment */
-/* clang-format off */
-
-#define MM_FLAG_COMMIT 0x01
-#define MM_FLAG_UNMAP 0x02
-#define MM_FLAG_STAGE1 0x04
-
-/* clang-format on */
-
static struct mm_ptable ptable;
static struct spinlock ptable_lock;
@@ -210,9 +198,19 @@
}
/**
+ * Returns the first address which cannot be encoded in page tables given by
+ * `flags`. It is the exclusive end of the address space created by the tables.
+ */
+ptable_addr_t mm_ptable_addr_space_end(int flags)
+{
+ return mm_root_table_count(flags) *
+ mm_entry_size(mm_max_level(flags) + 1);
+}
+
+/**
* Initialises the given page table.
*/
-static bool mm_ptable_init(struct mm_ptable *t, int flags, struct mpool *ppool)
+bool mm_ptable_init(struct mm_ptable *t, int flags, struct mpool *ppool)
{
uint8_t i;
size_t j;
@@ -492,8 +490,7 @@
struct mpool *ppool)
{
uint8_t root_level = mm_max_level(flags) + 1;
- ptable_addr_t ptable_end =
- mm_root_table_count(flags) * mm_entry_size(root_level);
+ ptable_addr_t ptable_end = mm_ptable_addr_space_end(flags);
ptable_addr_t end = mm_round_up_to_page(pa_addr(pa_end));
ptable_addr_t begin = pa_addr(arch_mm_clear_pa(pa_begin));