fix: pass ns bit to tlb invalidate
From Arm ARM I.a D8.13.5 TLB maintenance instructions I_CPNYZ,
"For TLB maintenance instructions that take a register argument that
holds an IPA and that do not apply to a range of addresses, the register
specified by the Xt argument has the following format:
Register bit[63] is one of the following:
-If the instruction is executed in Secure state, the NS bit specifying
the Secure or Non-secure IPA space.
-If the instruction is executed in Non-secure state, RES 0."
The mm library is missing specifying the security state for S2 TLB
invalidation by IPA. It means S2 TLB invalidation operations always
apply to the secure IPA space. This change conveys a parameter
specifying if the S2 TLB operation applies to the secure or NS IPA
space, resulting in invalidating pages from the appropriate IPA space.
Change-Id: Iba2449112ffad0c1fc1fc460c2a67600075df743
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
diff --git a/inc/hf/arch/mm.h b/inc/hf/arch/mm.h
index ed7d690..8cc3d7e 100644
--- a/inc/hf/arch/mm.h
+++ b/inc/hf/arch/mm.h
@@ -105,7 +105,7 @@
* Invalidates the given range of stage-2 TLB.
*/
void arch_mm_invalidate_stage2_range(uint16_t vmid, ipaddr_t va_begin,
- ipaddr_t va_end);
+ ipaddr_t va_end, bool non_secure);
/**
* Writes back the given range of virtual memory to such a point that all cores