fix: fix build with clang-18
Some uses of inline assembly for accessing floating point registers did
not enable the FP extension and were failing with clang-18.
The check in the linker script for the `hftest_enable` variable fails
under clang-18. However, hftest still compiles and passes without the
check, so it was removed.
Fix new warnings from `clang-tidy`.
Apply `make format`.
Change-Id: I43996abb4c42de54be807dcdb76107b9752c62fb
Signed-off-by: Karl Meakin <karl.meakin@arm.com>
diff --git a/src/api.c b/src/api.c
index fefee61..bb3bba7 100644
--- a/src/api.c
+++ b/src/api.c
@@ -4723,6 +4723,7 @@
* 64bit and less than v1.2: 6 registers
* 64bit and v1.2 or greater: 16 registers
*/
+ /* NOLINTNEXTLINE(readability-avoid-nested-conditional-operator) */
const size_t registers_max = log32 ? 6 : (v1_2 ? 16 : 6);
const size_t chars_max =
registers_max * (log32 ? sizeof(uint32_t) : sizeof(uint64_t));
diff --git a/src/arch/aarch64/hypervisor/fpu.c b/src/arch/aarch64/hypervisor/fpu.c
index 64c877d..fe972d4 100644
--- a/src/arch/aarch64/hypervisor/fpu.c
+++ b/src/arch/aarch64/hypervisor/fpu.c
@@ -13,14 +13,17 @@
void arch_fpu_state_save_to_vcpu(struct vcpu *vcpu)
{
__asm__ volatile(
+ ".arch_extension fp;"
"mrs %0, fpsr;"
- "mrs %1, fpcr"
+ "mrs %1, fpcr;"
+ ".arch_extension nofp;"
: "=r"(vcpu->regs.fpsr), "=r"(vcpu->regs.fpcr));
}
void arch_fpu_regs_save_to_vcpu(struct vcpu *vcpu)
{
__asm__ volatile(
+ ".arch_extension fp;"
"stp q0, q1, [%0], #32;"
"stp q2, q3, [%0], #32;"
"stp q4, q5, [%0], #32;"
@@ -36,7 +39,8 @@
"stp q24, q25, [%0], #32;"
"stp q26, q27, [%0], #32;"
"stp q28, q29, [%0], #32;"
- "stp q30, q31, [%0], #32"
+ "stp q30, q31, [%0], #32;"
+ ".arch_extension nofp;"
:
: "r"(&vcpu->regs.fp));
}
@@ -50,8 +54,10 @@
void arch_fpu_state_restore_from_vcpu(struct vcpu *vcpu)
{
__asm__ volatile(
+ ".arch_extension fp;"
"msr fpsr, %0;"
- "msr fpcr, %1"
+ "msr fpcr, %1;"
+ ".arch_extension nofp;"
:
: "r"(vcpu->regs.fpsr), "r"(vcpu->regs.fpcr));
}
@@ -59,6 +65,7 @@
void arch_fpu_regs_restore_from_vcpu(struct vcpu *vcpu)
{
__asm__ volatile(
+ ".arch_extension fp;"
"ldp q0, q1, [%0], #32;"
"ldp q2, q3, [%0], #32;"
"ldp q4, q5, [%0], #32;"
@@ -74,7 +81,8 @@
"ldp q24, q25, [%0], #32;"
"ldp q26, q27, [%0], #32;"
"ldp q28, q29, [%0], #32;"
- "ldp q30, q31, [%0], #32"
+ "ldp q30, q31, [%0], #32;"
+ ".arch_extension nofp;"
:
: "r"(&vcpu->regs.fp));
}
diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
index 3c04e1f..1a37562 100644
--- a/src/arch/aarch64/mm.c
+++ b/src/arch/aarch64/mm.c
@@ -857,8 +857,7 @@
nsa_nsw = 0;
}
- arch_mm_config = (struct arch_mm_config)
- {
+ arch_mm_config = (struct arch_mm_config){
.ttbr0_el2 = pa_addr(table),
.vtcr_el2 = (1U << 31) | /* RES1. */
@@ -879,11 +878,11 @@
* 0xf0 -> Tagged Normal, Inner/Outer Write-Back,
* Read/Write-Alloc non-transient memory.
*/
- .mair_el2 = (0 << (8 * STAGE1_DEVICEINDX)) |
+ .mair_el2 = (0 << (8 * STAGE1_DEVICEINDX)) |
#if ENABLE_MTE
- (0xf0 << (8 * STAGE1_STACKINDX)) |
+ (0xf0 << (8 * STAGE1_STACKINDX)) |
#endif
- (0xff << (8 * STAGE1_NORMALINDX)),
+ (0xff << (8 * STAGE1_NORMALINDX)),
.sctlr_el2 = get_sctlr_el2_value(false),
.vstcr_el2 = (1U << 31) | /* RES1. */
diff --git a/src/arch/aarch64/plat/interrupts/gicv3_helpers.h b/src/arch/aarch64/plat/interrupts/gicv3_helpers.h
index a5a66be..38e2f69 100644
--- a/src/arch/aarch64/plat/interrupts/gicv3_helpers.h
+++ b/src/arch/aarch64/plat/interrupts/gicv3_helpers.h
@@ -35,22 +35,23 @@
*/
#if GIC_EXT_INTID
/* GICv3.1 */
-#define GICD_OFFSET_8(REG, id) \
- (((id) <= MAX_SPI_ID) ? GICD_##REG##R + (uintptr_t)(id) \
- : GICD_##REG##RE + (uintptr_t)(id)-MIN_ESPI_ID)
+#define GICD_OFFSET_8(REG, id) \
+ (((id) <= MAX_SPI_ID) \
+ ? GICD_##REG##R + (uintptr_t)(id) \
+ : GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID)
-#define GICD_OFFSET(REG, id) \
- (((id) <= MAX_SPI_ID) \
- ? GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) \
- : GICD_##REG##RE + \
- ((((uintptr_t)(id)-MIN_ESPI_ID) >> REG##R_SHIFT) \
+#define GICD_OFFSET(REG, id) \
+ (((id) <= MAX_SPI_ID) \
+ ? GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) \
+ : GICD_##REG##RE + \
+ ((((uintptr_t)(id) - MIN_ESPI_ID) >> REG##R_SHIFT) \
<< 2))
-#define GICD_OFFSET_64(REG, id) \
- (((id) <= MAX_SPI_ID) \
- ? GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) \
- : GICD_##REG##RE + \
- ((((uintptr_t)(id)-MIN_ESPI_ID) >> REG##R_SHIFT) \
+#define GICD_OFFSET_64(REG, id) \
+ (((id) <= MAX_SPI_ID) \
+ ? GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) \
+ : GICD_##REG##RE + \
+ ((((uintptr_t)(id) - MIN_ESPI_ID) >> REG##R_SHIFT) \
<< 3))
#else /* GICv3 */
diff --git a/src/dlog.c b/src/dlog.c
index 5a12327..780cf55 100644
--- a/src/dlog.c
+++ b/src/dlog.c
@@ -393,7 +393,7 @@
}
break;
case length64:
- if ((int64_t)signed_value < 0) {
+ if (signed_value < 0) {
flags->neg = true;
signed_value = -signed_value;
}
diff --git a/src/ffa_memory.c b/src/ffa_memory.c
index 27e3b56..53a605f 100644
--- a/src/ffa_memory.c
+++ b/src/ffa_memory.c
@@ -618,8 +618,8 @@
bool comp_offset_lt_transaction_descriptor_size =
composite_offset_0 <
(sizeof(struct ffa_memory_region) +
- (uint32_t)(memory_region->memory_access_desc_size *
- memory_region->receiver_count));
+ (size_t)(memory_region->memory_access_desc_size *
+ memory_region->receiver_count));
bool comp_offset_with_comp_gt_fragment_length =
composite_offset_0 +
sizeof(struct ffa_composite_memory_region) >
@@ -3621,8 +3621,8 @@
composite_constituents_offset +
retrieved_constituents_count *
sizeof(struct ffa_memory_region_constituent) -
- (uint32_t)(memory_region->memory_access_desc_size *
- (memory_region->receiver_count - 1));
+ (size_t)(memory_region->memory_access_desc_size *
+ (memory_region->receiver_count - 1));
return expected_fragment_offset;
}