Trap access to ICC_SRE_EL1 as well.
Bug: 132960440
Change-Id: I3e81ee7bc138f1c2fb411ec6b429b41b9ff630e5
diff --git a/src/arch/aarch64/hypervisor/exceptions.S b/src/arch/aarch64/hypervisor/exceptions.S
index 009dc83..6a8309f 100644
--- a/src/arch/aarch64/hypervisor/exceptions.S
+++ b/src/arch/aarch64/hypervisor/exceptions.S
@@ -322,7 +322,8 @@
add x2, x1, #VCPU_GIC
mrs x3, ich_hcr_el2
- str x3, [x2, #16 * 0]
+ mrs x4, icc_sre_el2
+ stp x3, x4, [x2, #16 * 0]
#endif
/* Save floating point registers. */
@@ -476,8 +477,9 @@
/* Offset is too large, so start from a new base. */
add x2, x0, #VCPU_GIC
- ldr x3, [x2, #16 * 0]
+ ldp x3, x4, [x2, #16 * 0]
msr ich_hcr_el2, x3
+ msr icc_sre_el2, x4
#endif
/*