VHE: Redirect system register access when VHE is enabled.
Make accesses to all system registers affected by VHE condition on
build and CPU support for VHE.
Change-Id: I6c287993d2bb362d7aada02bcd979d289eced17f
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c
index fc82b1b..8c021f6 100644
--- a/src/arch/aarch64/hypervisor/handler.c
+++ b/src/arch/aarch64/hypervisor/handler.c
@@ -69,8 +69,15 @@
*/
void complete_saving_state(struct vcpu *vcpu)
{
- vcpu->regs.peripherals.cntv_cval_el0 = read_msr(cntv_cval_el0);
- vcpu->regs.peripherals.cntv_ctl_el0 = read_msr(cntv_ctl_el0);
+ if (has_vhe_support()) {
+ vcpu->regs.peripherals.cntv_cval_el0 =
+ read_msr(MSR_CNTV_CVAL_EL02);
+ vcpu->regs.peripherals.cntv_ctl_el0 =
+ read_msr(MSR_CNTV_CTL_EL02);
+ } else {
+ vcpu->regs.peripherals.cntv_cval_el0 = read_msr(cntv_cval_el0);
+ vcpu->regs.peripherals.cntv_ctl_el0 = read_msr(cntv_ctl_el0);
+ }
api_regs_state_saved(vcpu);
@@ -88,8 +95,14 @@
* then be latched in.
*/
write_msr(cnthp_ctl_el2, 0);
- write_msr(cnthp_cval_el2, read_msr(cntv_cval_el0));
- write_msr(cnthp_ctl_el2, read_msr(cntv_ctl_el0));
+
+ if (has_vhe_support()) {
+ write_msr(cnthp_cval_el2, read_msr(MSR_CNTV_CVAL_EL02));
+ write_msr(cnthp_ctl_el2, read_msr(MSR_CNTV_CTL_EL02));
+ } else {
+ write_msr(cnthp_cval_el2, read_msr(cntv_cval_el0));
+ write_msr(cnthp_ctl_el2, read_msr(cntv_ctl_el0));
+ }
}
}
@@ -103,9 +116,17 @@
* a spurious timer interrupt. This could be a problem if the interrupt
* is configured as edge-triggered, as it would then be latched in.
*/
- write_msr(cntv_ctl_el0, 0);
- write_msr(cntv_cval_el0, vcpu->regs.peripherals.cntv_cval_el0);
- write_msr(cntv_ctl_el0, vcpu->regs.peripherals.cntv_ctl_el0);
+ if (has_vhe_support()) {
+ write_msr(MSR_CNTV_CTL_EL02, 0);
+ write_msr(MSR_CNTV_CVAL_EL02,
+ vcpu->regs.peripherals.cntv_cval_el0);
+ write_msr(MSR_CNTV_CTL_EL02,
+ vcpu->regs.peripherals.cntv_ctl_el0);
+ } else {
+ write_msr(cntv_ctl_el0, 0);
+ write_msr(cntv_cval_el0, vcpu->regs.peripherals.cntv_cval_el0);
+ write_msr(cntv_ctl_el0, vcpu->regs.peripherals.cntv_ctl_el0);
+ }
/*
* If we are switching (back) to the primary, disable the EL2 physical
@@ -705,7 +726,8 @@
*/
static uintreg_t get_el1_exception_handler_addr(const struct vcpu *vcpu)
{
- uintreg_t base_addr = read_msr(vbar_el1);
+ uintreg_t base_addr = has_vhe_support() ? read_msr(MSR_VBAR_EL12)
+ : read_msr(vbar_el1);
uintreg_t pe_mode = vcpu->regs.spsr & PSR_PE_MODE_MASK;
bool is_arch32 = vcpu->regs.spsr & PSR_ARCH_MODE_32;
@@ -736,10 +758,17 @@
uintreg_t handler_address = get_el1_exception_handler_addr(vcpu);
/* Update the CPU state to inject the exception. */
- write_msr(esr_el1, esr_el1_value);
- write_msr(far_el1, far_el1_value);
- write_msr(elr_el1, vcpu->regs.pc);
- write_msr(spsr_el1, vcpu->regs.spsr);
+ if (has_vhe_support()) {
+ write_msr(MSR_ESR_EL12, esr_el1_value);
+ write_msr(MSR_FAR_EL12, far_el1_value);
+ write_msr(MSR_ELR_EL12, vcpu->regs.pc);
+ write_msr(MSR_SPSR_EL12, vcpu->regs.spsr);
+ } else {
+ write_msr(esr_el1, esr_el1_value);
+ write_msr(far_el1, far_el1_value);
+ write_msr(elr_el1, vcpu->regs.pc);
+ write_msr(spsr_el1, vcpu->regs.spsr);
+ }
/*
* Mask (disable) interrupts and run in EL1h mode.
diff --git a/src/arch/aarch64/inc/hf/arch/vm/timer.h b/src/arch/aarch64/inc/hf/arch/vm/timer.h
index ef4e453..2d6f0bf 100644
--- a/src/arch/aarch64/inc/hf/arch/vm/timer.h
+++ b/src/arch/aarch64/inc/hf/arch/vm/timer.h
@@ -11,13 +11,16 @@
#include <stdint.h>
#include "../msr.h"
+#include "../sysregs.h"
static inline void timer_set(uint32_t ticks)
{
- write_msr(CNTV_TVAL_EL0, ticks);
+ has_vhe_support() ? write_msr(MSR_CNTV_TVAL_EL02, ticks)
+ : write_msr(cntv_tval_el0, ticks);
}
static inline void timer_start(void)
{
- write_msr(CNTV_CTL_EL0, 0x00000001);
+ has_vhe_support() ? write_msr(MSR_CNTV_CTL_EL02, 0x00000001)
+ : write_msr(cntv_ctl_el0, 0x00000001);
}
diff --git a/src/arch/aarch64/timer.c b/src/arch/aarch64/timer.c
index 393e488..e2b6a16 100644
--- a/src/arch/aarch64/timer.c
+++ b/src/arch/aarch64/timer.c
@@ -17,6 +17,7 @@
#include "hf/addr.h"
#include "msr.h"
+#include "sysregs.h"
#define CNTV_CTL_EL0_ENABLE (1u << 0)
#define CNTV_CTL_EL0_IMASK (1u << 1)
@@ -114,7 +115,8 @@
*/
bool arch_timer_enabled_current(void)
{
- uintreg_t cntv_ctl_el0 = read_msr(cntv_ctl_el0);
+ uintreg_t cntv_ctl_el0 = has_vhe_support() ? read_msr(MSR_CNTV_CTL_EL02)
+ : read_msr(cntv_ctl_el0);
return (cntv_ctl_el0 & CNTV_CTL_EL0_ENABLE) &&
!(cntv_ctl_el0 & CNTV_CTL_EL0_IMASK);
@@ -125,7 +127,8 @@
*/
void arch_timer_disable_current(void)
{
- write_msr(cntv_ctl_el0, 0x0);
+ has_vhe_support() ? write_msr(MSR_CNTV_CTL_EL02, 0x0)
+ : write_msr(cntv_ctl_el0, 0x0);
}
/**
@@ -135,7 +138,9 @@
*/
static uint64_t arch_timer_remaining_ticks_current(void)
{
- uintreg_t cntv_cval_el0 = read_msr(cntv_cval_el0);
+ uintreg_t cntv_cval_el0 = has_vhe_support()
+ ? read_msr(MSR_CNTV_CVAL_EL02)
+ : read_msr(cntv_cval_el0);
uintreg_t cntvct_el0 = read_msr(cntvct_el0);
if (cntv_cval_el0 >= cntvct_el0) {