commit e6e1db03f5eafcaaeccdb51974668d50536f2026
author Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Fri May 16 10:45:20 2025 +0100
committer Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Fri May 16 10:49:10 2025 +0100
tree 058925e883e216283dec9a2bd8c272941d41b30d
parent 6abc66ca30630e4b49e38a30e7a39977b9884f04

RSE: Add ROM SRAM copy build config

Add a new build config which builds the RSE using the MinSizeRel
CMAKE_BUILD_TYPE and specifies that the RSE should copy the ROM code to
SRAM and execute it there.

Note that we can only use the MinSizeRel build type when using this
config flag, as this requires the BL1_1 code to be smaller than the SRAM
size.

Change-Id: Ie5c7e4a4997767dcdf9ef4e192954bed8f4fc37f
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

build_helper/build_helper_config_maps.py

diff --git a/build_helper/build_helper_config_maps.py b/build_helper/build_helper_config_maps.py
index a6dbe6a..2ddb045 100644
--- a/build_helper/build_helper_config_maps.py
+++ b/build_helper/build_helper_config_maps.py
@@ -155,7 +155,10 @@
                                    "-DEXTRA_NS_TEST_SUITE_PATH=%(codebase_root_dir)s/../tf-m-extras/partitions/measured_boot/test/non_secure "),
 
     # Provisioning blob signing
-    "RSE_PROVISIONING_ASYMMETRIC" : ("-DRSE_SYMMETRIC_PROVISIONING=OFF")
+    "RSE_PROVISIONING_ASYMMETRIC" : ("-DRSE_SYMMETRIC_PROVISIONING=OFF"),
+
+    # Copy ROM code to SRAM in BL1_2 and execute from there
+    "RSE_COPY_USE_ROM_LIB_IN_SRAM" : ("-DRSE_USE_ROM_LIB_FROM_SRAM=ON")
 }
 
 mapTfmExtrasExamplePaths = {

build_helper/build_helper_configs.py

diff --git a/build_helper/build_helper_configs.py b/build_helper/build_helper_configs.py
index 2e5a9b2..8d65d3e 100755
--- a/build_helper/build_helper_configs.py
+++ b/build_helper/build_helper_configs.py
@@ -410,6 +410,9 @@
                     # RSE_TC4_GCC_2_Release_BL2_ATTESTATION_SCHEME_CCA
                     ("arm/rse/tc/tc4", "GCC_10_3", "2",
                      "OFF", "OFF", "Release", True, "", "ATTESTATION_SCHEME_CCA"),
+                    # RSE_TC4_GCC_2_RegS_RegNS_MinSizeRel_BL2_RSE_COPY_USE_ROM_LIB_IN_SRAM
+                    ("arm/rse/tc/tc4", "GCC_10_3", "2",
+                     "RegS, RegNS", "OFF", "MinSizeRel", True, "", "RSE_COPY_USE_ROM_LIB_IN_SRAM"),
                     # RSE_RDV3_GCC_2_Release_BL2_NSOFF_CFG0
                     ("arm/rse/neoverse_rd/rdv3", "GCC_10_3", "2",
                      "OFF", "OFF", "Release", True, "", "NSOFF, CFG0"),
@@ -1124,6 +1127,10 @@
                     # BL1_1 tests only support symmetric provisioning config
                     ("arm/rse/tc/tc4", "*", "*", "RegBL1_1", "*",
                      "*", True, "*", "RSE_PROVISIONING_ASYMMETRIC"),
+                ],
+                "valid": [
+                    ("arm/rse/tc/tc4", "*", "*", "*", "*",
+                     "MinSizeRel", True, "*", "RSE_COPY_USE_ROM_LIB_IN_SRAM"),
                 ]
                 }