Lava: Update FVP parameters for RSE
Update to match the required addresses in
Ib27ceef3ed0402f447b25b5debbb8d2991ad97aeY, where the message loading
address is moved into the reset-persistent part of the SRAM and the
cookie for the persistent data area is moved into the GRETREG.
Change-Id: I7a78d26b521017ab527cd769f92e0bc305a56926
Signed-off-by: Raef Coles <raef.coles@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
diff --git a/build_helper/build_helper_configs.py b/build_helper/build_helper_configs.py
index 519efc7..5bcb225 100755
--- a/build_helper/build_helper_configs.py
+++ b/build_helper/build_helper_configs.py
@@ -107,7 +107,8 @@
"arm/rse/tc/tc3": ("if [ -f \"%(ci_build_root_dir)s/spe/bin/rse_bl1_tests.bin\" ]; then "
"cp %(ci_build_root_dir)s/spe/bin/rse_bl1_tests.bin %(ci_build_root_dir)s/spe/bin/sram.bin;"
"else "
- "cp %(ci_build_root_dir)s/spe/bin/provisioning/combined_provisioning_message.bin %(ci_build_root_dir)s/spe/bin/sram.bin;"
+ # dummy file with no data to keep the FVP happy
+ "touch %(ci_build_root_dir)s/spe/bin/sram.bin;"
"fi;"
"srec_cat "
"%(ci_build_root_dir)s/spe/bin/bl1_1.bin -Binary -offset 0x0 "
@@ -127,7 +128,8 @@
"arm/rse/tc/tc4": ("if [ -f \"%(ci_build_root_dir)s/spe/bin/rse_bl1_tests.bin\" ]; then "
"cp %(ci_build_root_dir)s/spe/bin/rse_bl1_tests.bin %(ci_build_root_dir)s/spe/bin/sram.bin;"
"else "
- "cp %(ci_build_root_dir)s/spe/bin/provisioning/combined_provisioning_message.bin %(ci_build_root_dir)s/spe/bin/sram.bin;"
+ # dummy file with no data to keep the FVP happy
+ "touch %(ci_build_root_dir)s/spe/bin/sram.bin;"
"fi;"
"srec_cat "
"%(ci_build_root_dir)s/spe/bin/bl1_1.bin -Binary -offset 0x0 "
@@ -236,10 +238,12 @@
"tfm_sign.bin"],
"arm/rse/tc/tc3": [
"%(ci_build_root_dir)s/spe/bin/rom.bin",
+ "%(ci_build_root_dir)s/spe/bin/provisioning/combined_provisioning_message.bin",
"%(ci_build_root_dir)s/spe/bin/sram.bin",
"%(ci_build_root_dir)s/spe/bin/host_flash.bin"],
"arm/rse/tc/tc4": [
"%(ci_build_root_dir)s/spe/bin/rom.bin",
+ "%(ci_build_root_dir)s/spe/bin/provisioning/combined_provisioning_message.bin",
"%(ci_build_root_dir)s/spe/bin/sram.bin",
"%(ci_build_root_dir)s/spe/bin/host_flash.bin"]
}
diff --git a/lava_helper/jinja2_templates/fvp_rse_tc3.jinja2 b/lava_helper/jinja2_templates/fvp_rse_tc3.jinja2
index 3608b4c..d325f91 100644
--- a/lava_helper/jinja2_templates/fvp_rse_tc3.jinja2
+++ b/lava_helper/jinja2_templates/fvp_rse_tc3.jinja2
@@ -40,7 +40,9 @@
arguments:
- "--simlimit 900"
- "-C css.sms.rse.rom.raw_image={ROM}"
+ - "-C css.sms.rse.GRETREG_RESET=0x1"
- "--data css.sms.rse.sram0={SRAM}@0x400"
+ - "--data css.sms.rse.sram1={COMBINED_PROVISIONING_MESSAGE}@0x5000"
- "-C board.flashloader0.fname={FLASH}"
- "-C displayController=2"
- "-C css.sms.rse.sic.SIC_AUTH_ENABLE=1"
diff --git a/lava_helper/jinja2_templates/fvp_rse_tc4.jinja2 b/lava_helper/jinja2_templates/fvp_rse_tc4.jinja2
index 3c7edc2..52583e4 100644
--- a/lava_helper/jinja2_templates/fvp_rse_tc4.jinja2
+++ b/lava_helper/jinja2_templates/fvp_rse_tc4.jinja2
@@ -40,7 +40,9 @@
arguments:
- "--simlimit 900"
- "-C css.sms.rse.rom.raw_image={ROM}"
+ - "-C css.sms.rse.GRETREG_RESET=0x1"
- "--data css.sms.rse.sram0={SRAM}@0x400"
+ - "--data css.sms.rse.sram1={COMBINED_PROVISIONING_MESSAGE}@0x5000"
- "-C board.flashloader0.fname={FLASH}"
- "-C displayController=2"
- "-C css.sms.rse.sic.SIC_AUTH_ENABLE=1"
diff --git a/lava_helper/lava_helper_configs.py b/lava_helper/lava_helper_configs.py
index 7cb6356..4457699 100644
--- a/lava_helper/lava_helper_configs.py
+++ b/lava_helper/lava_helper_configs.py
@@ -344,6 +344,9 @@
"rom": {
"data": "spe/bin/rom.bin"
},
+ "combined_provisioning_message": {
+ "data": "spe/bin/provisioning/combined_provisioning_message.bin"
+ },
"sram": {
"data": "spe/bin/sram.bin"
},
@@ -372,6 +375,9 @@
"rom": {
"data": "spe/bin/rom.bin"
},
+ "combined_provisioning_message": {
+ "data": "spe/bin/provisioning/combined_provisioning_message.bin"
+ },
"sram": {
"data": "spe/bin/sram.bin"
},