diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 46333af2d5..4704d3942d 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -43,23 +43,6 @@ static int32_t smccc_arch_features(u_register_t arg1)
 #if WORKAROUND_CVE_2018_3639
 	case SMCCC_ARCH_WORKAROUND_2: {
 #if DYNAMIC_WORKAROUND_CVE_2018_3639
-		unsigned long long ssbs;
-
-		/*
-		 * Firmware doesn't have to carry out dynamic workaround if the
-		 * PE implements architectural Speculation Store Bypass Safe
-		 * (SSBS) feature.
-		 */
-		ssbs = (read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
-			ID_AA64PFR1_EL1_SSBS_MASK;
-
-		/*
-		 * If architectural SSBS is available on this PE, no firmware
-		 * mitigation via SMCCC_ARCH_WORKAROUND_2 is required.
-		 */
-		if (ssbs != SSBS_NOT_IMPLEMENTED)
-			return 1;
-
 		/*
 		 * On a platform where at least one CPU requires
 		 * dynamic mitigation but others are either unaffected
