test(spm): add SVE+SME+SME_FA64 test configuration
Add SPM test config for testing the combination of FEAT_SVE + FEAT_SME
+FEAT_SME_FA64 arch. extensions.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib2c99a9ab083e3500f3f3118e8b1a47381c87a82
diff --git a/group/spm-l2-boot-tests/fvp-default,fvp-spm-sve+sme2,fvp-default:fvp-spm.sve+sme+fa64 b/group/spm-l2-boot-tests/fvp-default,fvp-spm-sve+sme2,fvp-default:fvp-spm.sve+sme+fa64
new file mode 100644
index 0000000..87ad7f5
--- /dev/null
+++ b/group/spm-l2-boot-tests/fvp-default,fvp-spm-sve+sme2,fvp-default:fvp-spm.sve+sme+fa64
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/run_config/fvp-spm.sve+sme+fa64 b/run_config/fvp-spm.sve+sme+fa64
new file mode 100644
index 0000000..089ed3a
--- /dev/null
+++ b/run_config/fvp-spm.sve+sme+fa64
@@ -0,0 +1,42 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+generate_lava_job_template() {
+ payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" file="tftf.exp" track_expect
+ uart="1" file="hold_uart.exp" track_expect
+
+ # SPM(reference implementation of S-EL2 firmware) has SMMUv3 driver
+ # enabled to help with stage-2 translation and virtualization of
+ # upstream peripheral devices. Hence, enable the SMMUv3 IP in FVP
+ # by configuring the appropriate parameters of the SMMUv3 AEM.
+
+ model="$model" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ has_smmuv3_params="1" \
+ memory_tagging_support_level="2" \
+ has_sve="1" \
+ has_sme="1" \
+ has_sme_fa64="1" \
+ gicd_are_fixed_one="1" \
+ gicv3_ext_interrupt_range="1" \
+ gicd_ext_ppi_count="64" \
+ gicd_ext_spi_count="1024" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}