)]}'
{
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        "time": "Thu Apr 02 15:26:43 2026 +0100"
      },
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        "email": "qwandor@google.com",
        "time": "Thu Apr 02 15:26:43 2026 +0100"
      },
      "message": "Prepare for 0.2.1 release.\n\nChange-Id: Ibe30c0d482dabc7c7de59bafd31e8f100ea973b1\nSigned-off-by: Andrew Walbran \u003cqwandor@google.com\u003e\n"
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        "email": "qwandor@google.com",
        "time": "Thu Apr 02 12:49:16 2026 +0100"
      },
      "message": "Show features in docs.rs build.\n\nChange-Id: I3365f0dab1fbcfb277c726e1d35d8c14b966345e\nSigned-off-by: Andrew Walbran \u003cqwandor@google.com\u003e\n"
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        "time": "Thu Apr 02 12:43:49 2026 +0100"
      },
      "committer": {
        "name": "Andrew Walbran",
        "email": "qwandor@google.com",
        "time": "Thu Apr 02 12:47:24 2026 +0100"
      },
      "message": "Implement embedded-hal Delay trait.\n\nThe dependency is optional, so can be avoided if desired.\n\nChange-Id: Ib15cdf01b2588a98f16e253a8a238ed25f72fac0\nSigned-off-by: Andrew Walbran \u003cqwandor@google.com\u003e\n"
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        "email": "imre.kis@arm.com",
        "time": "Tue Mar 31 15:40:02 2026 +0200"
      },
      "committer": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Thu Apr 02 13:32:50 2026 +0200"
      },
      "message": "Implement system register based timers\n\nAdd sysregs module that implements system register based timer drivers.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: I66c659a42896492a2806a33318b0a344a4983d1d\n"
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        "time": "Tue Mar 31 15:07:52 2026 +0200"
      },
      "committer": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Thu Apr 02 13:32:31 2026 +0200"
      },
      "message": "Move memory mapped timers into separate module\n\nMove the MMIO register definitions and driver implementations into\nseparate module.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: I293077b2fa84674836b68c1c552c8420b6ae7adf\n"
    },
    {
      "commit": "c3d935a435ce425572da4ed154547234ecd9fac3",
      "tree": "f054c05fb3b9bbb60aa714db18f7ebeefe98c8c2",
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        "email": "imre.kis@arm.com",
        "time": "Fri Mar 27 16:25:11 2026 +0100"
      },
      "committer": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Thu Apr 02 13:32:03 2026 +0200"
      },
      "message": "Add Timer abstraction layer\n\nIntroduce TimerInterface trait for accessing timer registers and\ngeneric Timer logic.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: I9c37a2e68369964f6a273ebf9139d8716ea8e5c4\n"
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        "email": "qwandor@google.com",
        "time": "Thu Apr 02 12:03:46 2026 +0100"
      },
      "committer": {
        "name": "Andrew Walbran",
        "email": "qwandor@google.com",
        "time": "Thu Apr 02 12:07:46 2026 +0100"
      },
      "message": "Update to Rust 2024 edition.\n\nChange-Id: Iea5412940bfc83eae957eaf1a2611a916ed57ee4\nSigned-off-by: Andrew Walbran \u003cqwandor@google.com\u003e\n"
    },
    {
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        "email": "imre.kis@arm.com",
        "time": "Fri Mar 27 16:15:35 2026 +0100"
      },
      "committer": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Tue Mar 31 16:19:05 2026 +0200"
      },
      "message": "Update dependencies\n\nUpdating safe-mmio to 0.3 changes the external API of this crate. This\nmeans that it is also necessary to increment arm-generic-timer minor\nversion.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: I2ea166b09c9af0dbbcb6994ba65ec17f17b6cf4b\n"
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    {
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      "author": {
        "name": "Andrew Walbran",
        "email": "qwandor@google.com",
        "time": "Mon Nov 10 17:44:13 2025 +0000"
      },
      "committer": {
        "name": "Andrew Walbran",
        "email": "qwandor@google.com",
        "time": "Mon Nov 10 17:44:13 2025 +0000"
      },
      "message": "Configure Dependabot.\n\nChange-Id: I7eccedf2aaa5d7e88e42466f3fa86845e26c6814\nSigned-off-by: Andrew Walbran \u003cqwandor@google.com\u003e\n"
    },
    {
      "commit": "baec74ca7597ea0cf4d95751cfdc23fad4833188",
      "tree": "cf397423c60fd5a95a8d41c30d8bf9ffbf8901c7",
      "parents": [
        "db5d9567fb842d77e3fcdd4ea3d8310730e8a7ef"
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      "author": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Thu Aug 14 18:02:07 2025 +0200"
      },
      "committer": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Thu Aug 14 20:13:05 2025 +0200"
      },
      "message": "Update repository URL and dependencies\n\nChange URL in Cargo.toml and in README.md to point to the new repository\nunder the arm-firmware-crates namespace. Also update dependencies and\nbump version number.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: I0fc0274ea39c139c5ba4c851c046ce3b48c9606c\n"
    },
    {
      "commit": "db5d9567fb842d77e3fcdd4ea3d8310730e8a7ef",
      "tree": "c35fbbec61a18db79b237e69cc9e6530f1cf2145",
      "parents": [
        "2dd2a4966e8f72c77bd0fe25363d7082a4f8df1d"
      ],
      "author": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Fri Aug 01 16:36:01 2025 +0200"
      },
      "committer": {
        "name": "Imre Kis",
        "email": "imre.kis@arm.com",
        "time": "Tue Aug 12 16:07:44 2025 +0200"
      },
      "message": "Initial implementation of the Arm generic timer driver\n\nThe implementation provides register descriptions and drivers for the\nCNTControlBase, CNTCTLBase, CNTReadBase, CNTBaseN, CNTEL0BaseN frames.\nIt also implements blocking and interrupt based timer wait functions.\n\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\nChange-Id: Ie0f06bfc1e35d38c3e4929fe2288dc510b8cd8ee\n"
    },
    {
      "commit": "2dd2a4966e8f72c77bd0fe25363d7082a4f8df1d",
      "tree": "4b825dc642cb6eb9a060e54bf8d69288fbee4904",
      "parents": [],
      "author": {
        "name": "Balint Dobszay",
        "email": "balint.dobszay@arm.com",
        "time": "Tue Aug 05 14:27:43 2025 +0200"
      },
      "committer": {
        "name": "Balint Dobszay",
        "email": "balint.dobszay@arm.com",
        "time": "Tue Aug 05 14:27:43 2025 +0200"
      },
      "message": "Initial empty commit\n\nSigned-off-by: Balint Dobszay \u003cbalint.dobszay@arm.com\u003e\n"
    }
  ]
}