blob: 39d89e33a0ef8eebc7b9e5600768fdd8149b00a1 [file] [log] [blame]
Soby Mathewb4c6df42022-11-09 11:13:29 +00001/*
2 * SPDX-License-Identifier: BSD-3-Clause
3 * SPDX-FileCopyrightText: Copyright TF-RMM Contributors.
4 */
5
6/* TODO: This file will need clean up */
7
8#ifndef ARCH_HELPERS_H
9#define ARCH_HELPERS_H
10
11#include <arch.h>
12#include <instr_helpers.h>
13#include <stdbool.h>
14#include <stddef.h>
15
16/* Define read function for system register */
17#define DEFINE_SYSREG_READ_FUNC(_name) \
18 DEFINE_SYSREG_READ_FUNC_(_name, _name)
19
20/* Define read & write function for system register */
21#define DEFINE_SYSREG_RW_FUNCS(_name) \
22 DEFINE_SYSREG_READ_FUNC_(_name, _name) \
23 DEFINE_SYSREG_WRITE_FUNC_(_name, _name)
24
25/* Define read & write function for renamed system register */
26#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
27 DEFINE_SYSREG_READ_FUNC_(_name, _reg_name) \
28 DEFINE_SYSREG_WRITE_FUNC_(_name, _reg_name)
29
30/* Define read function for renamed system register */
31#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
32 DEFINE_SYSREG_READ_FUNC_(_name, _reg_name)
33
34/* Define write function for renamed system register */
35#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
36 DEFINE_SYSREG_WRITE_FUNC_(_name, _reg_name)
37
38/*******************************************************************************
39 * TLB maintenance accessor prototypes
40 ******************************************************************************/
41DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
42DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
43DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
44DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
45DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
46DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1is)
47DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalls12e1)
48
49DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
50DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
Raghu Krishnamurthy0e15c3b2024-07-15 19:07:10 -070051DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2)
Soby Mathewb4c6df42022-11-09 11:13:29 +000052DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
53DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
54DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, ipas2e1is)
55
56/*******************************************************************************
57 * Cache maintenance accessor prototypes
58 ******************************************************************************/
59DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
60DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
61DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
62DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
63DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
64DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
65DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
Jean-Philippe Brucker6cfd0082025-01-22 17:15:56 +000066DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cipae)
AlexeiFedorov862f96c2024-03-01 16:26:48 +000067DEFINE_SYSOP_DCZVA
Soby Mathewb4c6df42022-11-09 11:13:29 +000068
69/*******************************************************************************
70 * Address translation accessor prototypes
71 ******************************************************************************/
72DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
73DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
74DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
75DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
76DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
77DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
78
79/*******************************************************************************
80 * Strip Pointer Authentication Code
81 ******************************************************************************/
82DEFINE_SYSOP_PARAM_FUNC(xpaci)
83
84/*******************************************************************************
85 * Cache management
86 ******************************************************************************/
87void flush_dcache_range(uintptr_t addr, size_t size);
88void clean_dcache_range(uintptr_t addr, size_t size);
89void inv_dcache_range(uintptr_t addr, size_t size);
Jean-Philippe Brucker6cfd0082025-01-22 17:15:56 +000090void flush_dcache_range_to_poe(uintptr_t paddr, size_t size);
Soby Mathewb4c6df42022-11-09 11:13:29 +000091
Arvind Ram Prakashbd36a1b2022-12-15 12:16:36 -060092#define is_dcache_enabled() ((read_sctlr_el2() & SCTLR_ELx_C_BIT) != 0UL)
Soby Mathewb4c6df42022-11-09 11:13:29 +000093
94/*******************************************************************************
95 * MMU management
96 ******************************************************************************/
Arvind Ram Prakashbd36a1b2022-12-15 12:16:36 -060097#define is_mmu_enabled() ((read_sctlr_el2() & SCTLR_ELx_M_BIT) != 0UL)
Soby Mathewb4c6df42022-11-09 11:13:29 +000098
99/*******************************************************************************
100 * FPU management
101 ******************************************************************************/
Arunachalam Ganapathy9ade18b2023-06-12 14:07:21 +0100102#define is_fpen_enabled() (EXTRACT(CPTR_EL2_VHE_FPEN, read_cptr_el2()) == \
103 CPTR_EL2_VHE_FPEN_NO_TRAP_11)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000104
105/*******************************************************************************
Arunachalam Ganapathyf6491212023-02-23 16:04:34 +0000106 * SVE management
107 ******************************************************************************/
Arunachalam Ganapathy9ade18b2023-06-12 14:07:21 +0100108#define is_zen_enabled() (EXTRACT(CPTR_EL2_VHE_ZEN, read_cptr_el2()) == \
109 CPTR_EL2_VHE_ZEN_NO_TRAP_11)
Arunachalam Ganapathyf6491212023-02-23 16:04:34 +0000110
111/*******************************************************************************
Arunachalam Ganapathy83f46ca2023-08-15 18:13:27 +0100112 * SME management
113 ******************************************************************************/
114#define is_smen_enabled() (EXTRACT(CPTR_EL2_SMEN, read_cptr_el2()) == \
115 CPTR_EL2_SMEN_NO_TRAP_11)
116
117/*******************************************************************************
Soby Mathewb4c6df42022-11-09 11:13:29 +0000118 * Misc. accessor prototypes
119 ******************************************************************************/
Soby Mathewb4c6df42022-11-09 11:13:29 +0000120#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
121#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
122
123DEFINE_SYSOP_FUNC(wfi)
124DEFINE_SYSOP_FUNC(wfe)
125DEFINE_SYSOP_FUNC(sev)
126DEFINE_SYSOP_FUNC(isb)
127
AlexeiFedorov4c7d4852024-01-25 14:37:34 +0000128/*******************************************************************************
129 * Stack Pointer Select
130 ******************************************************************************/
131#define write_spsel(val) SYSREG_WRITE_CONST(spsel, val)
132
133/*******************************************************************************
134 * Read Stack Pointer
135 ******************************************************************************/
136#define read_sp(var) READ_REGISTER(var, sp)
137
Soby Mathewb4c6df42022-11-09 11:13:29 +0000138static inline void enable_irq(void)
139{
140 /*
141 * The compiler memory barrier will prevent the compiler from
142 * scheduling non-volatile memory access after the write to the
143 * register.
144 *
145 * This could happen if some initialization code issues non-volatile
146 * accesses to an area used by an interrupt handler, in the assumption
147 * that it is safe as the interrupts are disabled at the time it does
148 * that (according to program order). However, non-volatile accesses
149 * are not necessarily in program order relatively with volatile inline
150 * assembly statements (and volatile accesses).
151 */
152 COMPILER_BARRIER();
153 write_daifclr(DAIF_IRQ_BIT);
154 isb();
155}
156
157static inline void enable_fiq(void)
158{
159 COMPILER_BARRIER();
160 write_daifclr(DAIF_FIQ_BIT);
161 isb();
162}
163
164static inline void enable_serror(void)
165{
166 COMPILER_BARRIER();
167 write_daifclr(DAIF_ABT_BIT);
168 isb();
169}
170
171static inline void enable_debug_exceptions(void)
172{
173 COMPILER_BARRIER();
174 write_daifclr(DAIF_DBG_BIT);
175 isb();
176}
177
178static inline void disable_irq(void)
179{
180 COMPILER_BARRIER();
181 write_daifset(DAIF_IRQ_BIT);
182 isb();
183}
184
185static inline void disable_fiq(void)
186{
187 COMPILER_BARRIER();
188 write_daifset(DAIF_FIQ_BIT);
189 isb();
190}
191
192static inline void disable_serror(void)
193{
194 COMPILER_BARRIER();
195 write_daifset(DAIF_ABT_BIT);
196 isb();
197}
198
199static inline void disable_debug_exceptions(void)
200{
201 COMPILER_BARRIER();
202 write_daifset(DAIF_DBG_BIT);
203 isb();
204}
205
206/*******************************************************************************
207 * System register accessor prototypes
208 ******************************************************************************/
209DEFINE_SYSREG_RW_FUNCS(sp_el0)
210DEFINE_SYSREG_RW_FUNCS(sp_el1)
211DEFINE_SYSREG_RW_FUNCS(elr_el12)
212DEFINE_SYSREG_RW_FUNCS(spsr_el12)
AlexeiFedoroveaec0c42023-02-01 18:13:32 +0000213
214DEFINE_SYSREG_RW_FUNCS(pmccfiltr_el0)
215DEFINE_SYSREG_RW_FUNCS(pmccntr_el0)
216DEFINE_SYSREG_RW_FUNCS(pmcntenclr_el0)
217DEFINE_SYSREG_RW_FUNCS(pmcntenset_el0)
218DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
219DEFINE_SYSREG_RW_FUNCS(pmintenclr_el1)
220DEFINE_SYSREG_RW_FUNCS(pmintenset_el1)
221DEFINE_SYSREG_RW_FUNCS(pmovsclr_el0)
222DEFINE_SYSREG_RW_FUNCS(pmovsset_el0)
223DEFINE_SYSREG_RW_FUNCS(pmselr_el0)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000224DEFINE_SYSREG_RW_FUNCS(pmuserenr_el0)
AlexeiFedoroveaec0c42023-02-01 18:13:32 +0000225DEFINE_SYSREG_RW_FUNCS(pmxevcntr_el0)
226DEFINE_SYSREG_RW_FUNCS(pmxevtyper_el0)
227
228DEFINE_SYSREG_RW_FUNCS(pmevcntr0_el0)
229DEFINE_SYSREG_RW_FUNCS(pmevcntr1_el0)
230DEFINE_SYSREG_RW_FUNCS(pmevcntr2_el0)
231DEFINE_SYSREG_RW_FUNCS(pmevcntr3_el0)
232DEFINE_SYSREG_RW_FUNCS(pmevcntr4_el0)
233DEFINE_SYSREG_RW_FUNCS(pmevcntr5_el0)
234DEFINE_SYSREG_RW_FUNCS(pmevcntr6_el0)
235DEFINE_SYSREG_RW_FUNCS(pmevcntr7_el0)
236DEFINE_SYSREG_RW_FUNCS(pmevcntr8_el0)
237DEFINE_SYSREG_RW_FUNCS(pmevcntr9_el0)
238DEFINE_SYSREG_RW_FUNCS(pmevcntr10_el0)
239DEFINE_SYSREG_RW_FUNCS(pmevcntr11_el0)
240DEFINE_SYSREG_RW_FUNCS(pmevcntr12_el0)
241DEFINE_SYSREG_RW_FUNCS(pmevcntr13_el0)
242DEFINE_SYSREG_RW_FUNCS(pmevcntr14_el0)
243DEFINE_SYSREG_RW_FUNCS(pmevcntr15_el0)
244DEFINE_SYSREG_RW_FUNCS(pmevcntr16_el0)
245DEFINE_SYSREG_RW_FUNCS(pmevcntr17_el0)
246DEFINE_SYSREG_RW_FUNCS(pmevcntr18_el0)
247DEFINE_SYSREG_RW_FUNCS(pmevcntr19_el0)
248DEFINE_SYSREG_RW_FUNCS(pmevcntr20_el0)
249DEFINE_SYSREG_RW_FUNCS(pmevcntr21_el0)
250DEFINE_SYSREG_RW_FUNCS(pmevcntr22_el0)
251DEFINE_SYSREG_RW_FUNCS(pmevcntr23_el0)
252DEFINE_SYSREG_RW_FUNCS(pmevcntr24_el0)
253DEFINE_SYSREG_RW_FUNCS(pmevcntr25_el0)
254DEFINE_SYSREG_RW_FUNCS(pmevcntr26_el0)
255DEFINE_SYSREG_RW_FUNCS(pmevcntr27_el0)
256DEFINE_SYSREG_RW_FUNCS(pmevcntr28_el0)
257DEFINE_SYSREG_RW_FUNCS(pmevcntr29_el0)
258DEFINE_SYSREG_RW_FUNCS(pmevcntr30_el0)
259
260DEFINE_SYSREG_RW_FUNCS(pmevtyper0_el0)
261DEFINE_SYSREG_RW_FUNCS(pmevtyper1_el0)
262DEFINE_SYSREG_RW_FUNCS(pmevtyper2_el0)
263DEFINE_SYSREG_RW_FUNCS(pmevtyper3_el0)
264DEFINE_SYSREG_RW_FUNCS(pmevtyper4_el0)
265DEFINE_SYSREG_RW_FUNCS(pmevtyper5_el0)
266DEFINE_SYSREG_RW_FUNCS(pmevtyper6_el0)
267DEFINE_SYSREG_RW_FUNCS(pmevtyper7_el0)
268DEFINE_SYSREG_RW_FUNCS(pmevtyper8_el0)
269DEFINE_SYSREG_RW_FUNCS(pmevtyper9_el0)
270DEFINE_SYSREG_RW_FUNCS(pmevtyper10_el0)
271DEFINE_SYSREG_RW_FUNCS(pmevtyper11_el0)
272DEFINE_SYSREG_RW_FUNCS(pmevtyper12_el0)
273DEFINE_SYSREG_RW_FUNCS(pmevtyper13_el0)
274DEFINE_SYSREG_RW_FUNCS(pmevtyper14_el0)
275DEFINE_SYSREG_RW_FUNCS(pmevtyper15_el0)
276DEFINE_SYSREG_RW_FUNCS(pmevtyper16_el0)
277DEFINE_SYSREG_RW_FUNCS(pmevtyper17_el0)
278DEFINE_SYSREG_RW_FUNCS(pmevtyper18_el0)
279DEFINE_SYSREG_RW_FUNCS(pmevtyper19_el0)
280DEFINE_SYSREG_RW_FUNCS(pmevtyper20_el0)
281DEFINE_SYSREG_RW_FUNCS(pmevtyper21_el0)
282DEFINE_SYSREG_RW_FUNCS(pmevtyper22_el0)
283DEFINE_SYSREG_RW_FUNCS(pmevtyper23_el0)
284DEFINE_SYSREG_RW_FUNCS(pmevtyper24_el0)
285DEFINE_SYSREG_RW_FUNCS(pmevtyper25_el0)
286DEFINE_SYSREG_RW_FUNCS(pmevtyper26_el0)
287DEFINE_SYSREG_RW_FUNCS(pmevtyper27_el0)
288DEFINE_SYSREG_RW_FUNCS(pmevtyper28_el0)
289DEFINE_SYSREG_RW_FUNCS(pmevtyper29_el0)
290DEFINE_SYSREG_RW_FUNCS(pmevtyper30_el0)
291
Soby Mathewb4c6df42022-11-09 11:13:29 +0000292DEFINE_SYSREG_RW_FUNCS(tpidrro_el0)
293DEFINE_SYSREG_RW_FUNCS(tpidr_el0)
294DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
295DEFINE_SYSREG_RW_FUNCS(csselr_el1)
296DEFINE_SYSREG_RW_FUNCS(sctlr_el12)
297DEFINE_SYSREG_RW_FUNCS(cpacr_el12)
Tushar Khandelwal59f673a2024-05-08 14:42:10 +0100298DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2)
Arunachalam Ganapathyf6491212023-02-23 16:04:34 +0000299DEFINE_RENAME_SYSREG_RW_FUNCS(zcr_el2, ZCR_EL2)
Arunachalam Ganapathy4f601e72023-05-22 11:49:29 +0100300DEFINE_RENAME_SYSREG_RW_FUNCS(zcr_el12, ZCR_EL12)
Arunachalam Ganapathy83f46ca2023-08-15 18:13:27 +0100301DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el2, SMCR_EL2)
302DEFINE_RENAME_SYSREG_RW_FUNCS(svcr, SVCR)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000303DEFINE_SYSREG_RW_FUNCS(ttbr0_el12)
304DEFINE_SYSREG_RW_FUNCS(ttbr1_el12)
305DEFINE_SYSREG_RW_FUNCS(tcr_el12)
306DEFINE_SYSREG_RW_FUNCS(esr_el12)
307DEFINE_SYSREG_RW_FUNCS(afsr0_el12)
308DEFINE_SYSREG_RW_FUNCS(afsr1_el12)
309DEFINE_SYSREG_RW_FUNCS(far_el12)
310DEFINE_SYSREG_RW_FUNCS(mair_el12)
311DEFINE_SYSREG_RW_FUNCS(vbar_el12)
312DEFINE_SYSREG_RW_FUNCS(contextidr_el12)
313DEFINE_SYSREG_RW_FUNCS(tpidr_el1)
314DEFINE_SYSREG_RW_FUNCS(amair_el12)
315DEFINE_SYSREG_RW_FUNCS(cntkctl_el12)
316DEFINE_SYSREG_RW_FUNCS(mdscr_el1)
317DEFINE_SYSREG_RW_FUNCS(mdccint_el1)
318DEFINE_SYSREG_RW_FUNCS(disr_el1)
319DEFINE_SYSREG_RW_FUNCS(cnrv_ctl_el02)
320DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
321DEFINE_SYSREG_RW_FUNCS(vsesr_el2)
322DEFINE_SYSREG_RW_FUNCS(par_el1)
323DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000324DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64AFR0_EL1, id_aa64afr0_el1)
325DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64AFR1_EL1, id_aa64afr1_el1)
AlexeiFedorov537bee02023-02-02 13:38:23 +0000326DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64DFR0_EL1, id_aa64dfr0_el1)
327DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64DFR1_EL1, id_aa64dfr1_el1)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000328DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64ISAR0_EL1, id_aa64isar0_el1)
329DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64ISAR1_EL1, id_aa64isar1_el1)
330DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1)
331DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64MMFR1_EL1, id_aa64mmfr1_el1)
AlexeiFedorov537bee02023-02-02 13:38:23 +0000332DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64MMFR2_EL1, id_aa64mmfr2_el1)
Javier Almansa Sobrinocfd32542024-10-09 19:38:56 +0100333DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64MMFR3_EL1, ID_AA64MMFR3)
334DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3)
AlexeiFedorov537bee02023-02-02 13:38:23 +0000335DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64PFR0_EL1, id_aa64pfr0_el1)
336DEFINE_RENAME_SYSREG_READ_FUNC(ID_AA64PFR1_EL1, id_aa64pfr1_el1)
AlexeiFedoroveaec0c42023-02-01 18:13:32 +0000337DEFINE_SYSREG_READ_FUNC(id_aa64afr0_el1)
338DEFINE_SYSREG_READ_FUNC(id_aa64afr1_el1)
339DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
340DEFINE_SYSREG_READ_FUNC(id_aa64dfr1_el1)
Arunachalam Ganapathyf6491212023-02-23 16:04:34 +0000341DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64zfr0_el1, ID_AA64ZFR0_EL1)
Arunachalam Ganapathy83f46ca2023-08-15 18:13:27 +0100342DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
AlexeiFedorov537bee02023-02-02 13:38:23 +0000343DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
AlexeiFedoroveaec0c42023-02-01 18:13:32 +0000344DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
AlexeiFedorov537bee02023-02-02 13:38:23 +0000345DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
346DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1)
347DEFINE_SYSREG_READ_FUNC(id_aa64mmfr2_el1)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000348DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
AlexeiFedoroveaec0c42023-02-01 18:13:32 +0000349DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
AlexeiFedorov537bee02023-02-02 13:38:23 +0000350DEFINE_RENAME_SYSREG_RW_FUNCS(mpam0_el1, MPAM0_EL1)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000351DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
352DEFINE_SYSREG_READ_FUNC(CurrentEl)
353DEFINE_SYSREG_READ_FUNC(ctr_el0)
354DEFINE_SYSREG_RW_FUNCS(daif)
355DEFINE_SYSREG_RW_FUNCS(spsr_el1)
356DEFINE_SYSREG_RW_FUNCS(spsr_el2)
357DEFINE_SYSREG_RW_FUNCS(elr_el1)
358DEFINE_SYSREG_RW_FUNCS(elr_el2)
359
360DEFINE_SYSREG_READ_FUNC(midr_el1)
361DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000362
363DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Javier Almansa Sobrinocfd32542024-10-09 19:38:56 +0100364DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000365
366DEFINE_SYSREG_RW_FUNCS(vbar_el1)
367DEFINE_SYSREG_RW_FUNCS(vbar_el2)
368
369DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
370DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
Javier Almansa Sobrinocfd32542024-10-09 19:38:56 +0100371DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el12, SCTLR2_EL12)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000372
373DEFINE_SYSREG_RW_FUNCS(actlr_el1)
374DEFINE_SYSREG_RW_FUNCS(actlr_el2)
375
376DEFINE_SYSREG_RW_FUNCS(esr_el1)
377DEFINE_SYSREG_RW_FUNCS(esr_el2)
378
379DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
380DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
381
382DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
383DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
384
385DEFINE_SYSREG_RW_FUNCS(far_el1)
386DEFINE_SYSREG_RW_FUNCS(far_el2)
387DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
388
389DEFINE_SYSREG_RW_FUNCS(mair_el1)
390DEFINE_SYSREG_RW_FUNCS(mair_el2)
391
392DEFINE_SYSREG_RW_FUNCS(amair_el1)
393DEFINE_SYSREG_RW_FUNCS(amair_el2)
394
395DEFINE_SYSREG_READ_FUNC(rvbar_el1)
396DEFINE_SYSREG_READ_FUNC(rvbar_el2)
397
398DEFINE_SYSREG_RW_FUNCS(rmr_el1)
399DEFINE_SYSREG_RW_FUNCS(rmr_el2)
400
401DEFINE_SYSREG_RW_FUNCS(tcr_el1)
402DEFINE_SYSREG_RW_FUNCS(tcr_el2)
403
404DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
405DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
406DEFINE_SYSREG_RW_FUNCS(ttbr1_el2)
407
408DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
409
410DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
411
412DEFINE_SYSREG_RW_FUNCS(cptr_el2)
413
414DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
415
416DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
417DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
418
419DEFINE_SYSREG_READ_FUNC(isr_el1)
420
421DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
422DEFINE_SYSREG_RW_FUNCS(hstr_el2)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000423DEFINE_SYSREG_RW_FUNCS(mpam2_el2)
424DEFINE_SYSREG_RW_FUNCS(mpamhcr_el2)
425DEFINE_SYSREG_RW_FUNCS(pmscr_el2)
426
Arunachalam Ganapathy4f601e72023-05-22 11:49:29 +0100427DEFINE_RENAME_SYSREG_RW_FUNCS(fpcr, FPCR)
428DEFINE_RENAME_SYSREG_RW_FUNCS(fpsr, FPSR)
429
AlexeiFedorov862f96c2024-03-01 16:26:48 +0000430DEFINE_SYSREG_READ_FUNC(dczid_el0)
431
Rustam Ismayilovb643b752024-09-27 16:29:46 +0200432DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
433
Javier Almansa Sobrino34005b92024-10-11 17:53:41 +0100434DEFINE_RENAME_SYSREG_READ_FUNC(gcscr_el12, ID_GCSCR_EL12)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000435/*******************************************************************************
436 * Timer register accessor prototypes
437 ******************************************************************************/
438DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
439DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
440DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
441DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
442DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
443DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
444DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
445DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
446DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
447DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
448DEFINE_SYSREG_READ_FUNC(cntpct_el0)
449DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
450DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el02)
451DEFINE_SYSREG_RW_FUNCS(cntp_cval_el02)
452DEFINE_SYSREG_RW_FUNCS(cntv_ctl_el02)
453DEFINE_SYSREG_RW_FUNCS(cntv_cval_el02)
454DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
455DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)
456
457/*******************************************************************************
458 * Interrupt Controller register accessor prototypes
459 ******************************************************************************/
460DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
461DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ctrl_el1, ICC_CTLR_EL1)
AlexeiFedoroveaec0c42023-02-01 18:13:32 +0000462DEFINE_RENAME_SYSREG_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1_EL1)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000463
464/*******************************************************************************
465 * Virtual GIC register accessor prototypes
466 ******************************************************************************/
467DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap0r0_el2, ICH_AP0R0_EL2)
468DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap0r1_el2, ICH_AP0R1_EL2)
469DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap0r2_el2, ICH_AP0R2_EL2)
470DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap0r3_el2, ICH_AP0R3_EL2)
471DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap1r0_el2, ICH_AP1R0_EL2)
472DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap1r1_el2, ICH_AP1R1_EL2)
473DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap1r2_el2, ICH_AP1R2_EL2)
474DEFINE_RENAME_SYSREG_RW_FUNCS(ich_ap1r3_el2, ICH_AP1R3_EL2)
475
476DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr0_el2, ICH_LR0_EL2)
477DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr1_el2, ICH_LR1_EL2)
478DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr2_el2, ICH_LR2_EL2)
479DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr3_el2, ICH_LR3_EL2)
480DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr4_el2, ICH_LR4_EL2)
481DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr5_el2, ICH_LR5_EL2)
482DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr6_el2, ICH_LR6_EL2)
483DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr7_el2, ICH_LR7_EL2)
484DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr8_el2, ICH_LR8_EL2)
485DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr9_el2, ICH_LR9_EL2)
486DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr10_el2, ICH_LR10_EL2)
487DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr11_el2, ICH_LR11_EL2)
488DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr12_el2, ICH_LR12_EL2)
489DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr13_el2, ICH_LR13_EL2)
490DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr14_el2, ICH_LR14_EL2)
491DEFINE_RENAME_SYSREG_RW_FUNCS(ich_lr15_el2, ICH_LR15_EL2)
492
493DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2)
494DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2)
495DEFINE_RENAME_SYSREG_READ_FUNC(ich_vtr_el2, ICH_VTR_EL2)
496DEFINE_RENAME_SYSREG_READ_FUNC(ich_misr_el2, ICH_MISR_EL2)
497
Soby Mathewb4c6df42022-11-09 11:13:29 +0000498/* Armv8.3 Pointer Authentication Registers */
499DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
500DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
Arvind Ram Prakashbd36a1b2022-12-15 12:16:36 -0600501DEFINE_RENAME_SYSREG_RW_FUNCS(apibkeyhi_el1, APIBKeyHi_EL1)
502DEFINE_RENAME_SYSREG_RW_FUNCS(apibkeylo_el1, APIBKeyLo_EL1)
503DEFINE_RENAME_SYSREG_RW_FUNCS(apdakeyhi_el1, APDAKeyHi_EL1)
504DEFINE_RENAME_SYSREG_RW_FUNCS(apdakeylo_el1, APDAKeyLo_EL1)
505DEFINE_RENAME_SYSREG_RW_FUNCS(apdbkeyhi_el1, APDBKeyHi_EL1)
506DEFINE_RENAME_SYSREG_RW_FUNCS(apdbkeylo_el1, APDBKeyLo_EL1)
507DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeyhi_el1, APGAKeyHi_EL1)
508DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1)
Soby Mathewb4c6df42022-11-09 11:13:29 +0000509
510/* Armv8.5 MTE Registers */
511DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
512DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
513DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
514DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
515
Arvind Ram Prakashbd36a1b2022-12-15 12:16:36 -0600516/* Armv8.5 Random Number Register */
517DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
518
Tushar Khandelwal59f673a2024-05-08 14:42:10 +0100519/* MEC Registers */
520DEFINE_RENAME_SYSREG_READ_FUNC(mecidr_el2, MECIDR_EL2)
521DEFINE_RENAME_SYSREG_RW_FUNCS(mecid_p0_el2, MECID_P0_EL2)
522DEFINE_RENAME_SYSREG_RW_FUNCS(mecid_a0_el2, MECID_A0_EL2)
523
524DEFINE_RENAME_SYSREG_RW_FUNCS(mecid_p1_el2, MECID_P1_EL2)
525DEFINE_RENAME_SYSREG_RW_FUNCS(mecid_a1_el2, MECID_A1_EL2)
526
527DEFINE_RENAME_SYSREG_RW_FUNCS(vmecid_p_el2, VMECID_P_EL2)
528DEFINE_RENAME_SYSREG_RW_FUNCS(vmecid_a_el2, VMECID_P_EL2)
529
530DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
531
Soby Mathewb4c6df42022-11-09 11:13:29 +0000532#endif /* ARCH_HELPERS_H */