fix(rmm): replace ARRAY_READ/WRITE macros with direct read/write
In sysregs.c 'rt' index of reads/writes from/to 'rec->regs[rt]'
is being checked for maximum possible value of 31 corresonding
to XZR and all these cases are handled safely, so there is no
need for using ARRAY_READ/WRITE macros which cause performance
deterioration.
This patch replaces usage of ARRAY_READ/WRITE macros with direct
read and writes commands and renames those macros to
SAFE_ARRAY_READ/WRITE.
The patch removes 'esr_sysreg_rt()' inline function
defined in esr.h and replaces calls to it with modified
ESR_EL2_SYSREG_ISS_RT macro.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ib2d9996ef380ffb9cdcafa320ded9fa991d9a378
diff --git a/lib/arch/include/arch.h b/lib/arch/include/arch.h
index a67baa4..5db3d08 100644
--- a/lib/arch/include/arch.h
+++ b/lib/arch/include/arch.h
@@ -882,10 +882,8 @@
#define ESR_EL2_SYSREG_IS_WRITE(esr) (!((esr) & ESR_EL2_SYSREG_DIRECTION))
#define ESR_IL(esr) ((esr) & ESR_EL2_IL_MASK)
-#define ESR_ISS(esr) ((esr) & ESR_EL2_ISS_MASK)
-#define ESR_EL2_SYSREG_ISS_RT(esr) \
- ((ESR_ISS(esr) & ESR_EL2_SYSREG_TRAP_RT_MASK) >> ESR_EL2_SYSREG_TRAP_RT_SHIFT)
+#define ESR_EL2_SYSREG_ISS_RT(esr) EXTRACT(ESR_EL2_SYSREG_TRAP_RT, esr)
#define ICC_HPPIR1_EL1_INTID_SHIFT 0
#define ICC_HPPIR1_EL1_INTID_WIDTH 24
diff --git a/lib/arch/include/esr.h b/lib/arch/include/esr.h
index a88b71c..da34f45 100644
--- a/lib/arch/include/esr.h
+++ b/lib/arch/include/esr.h
@@ -66,13 +66,4 @@
}
}
-/*
- * For a trapped msr/mrs sysreg access, get the transfer register in the
- * ESR_EL2.
- */
-static inline unsigned int esr_sysreg_rt(unsigned long esr)
-{
- return EXTRACT(ESR_EL2_SYSREG_TRAP_RT, esr);
-}
-
#endif /* ESR_H */
diff --git a/lib/common/include/utils_def.h b/lib/common/include/utils_def.h
index 2dc310a..604cd6e 100644
--- a/lib/common/include/utils_def.h
+++ b/lib/common/include/utils_def.h
@@ -85,7 +85,7 @@
* _i: index
* _v: variable/value to write
*/
-#define ARRAY_READ(_a, _i, _v) \
+#define SAFE_ARRAY_READ(_a, _i, _v) \
({ \
CHECK_ARRAY_TYPE(_a, _v); \
if (_i >= ARRAY_SIZE(_a)) { \
@@ -94,7 +94,7 @@
_v = _a[_i]; \
})
-#define ARRAY_WRITE(_a, _i, _v) \
+#define SAFE_ARRAY_WRITE(_a, _i, _v) \
({ \
CHECK_ARRAY_TYPE(_a, _v); \
if (_i >= ARRAY_SIZE(_a)) { \
diff --git a/runtime/core/sysregs.c b/runtime/core/sysregs.c
index 55fac96..af263ba 100644
--- a/runtime/core/sysregs.c
+++ b/runtime/core/sysregs.c
@@ -60,6 +60,7 @@
/*
* Read Rt value from the issued instruction,
* the general-purpose register used for the transfer.
+ * Rt bits [9:5] of ISS field cannot exceed 0b11111.
*/
rt = ESR_EL2_SYSREG_ISS_RT(esr);
@@ -93,8 +94,7 @@
mask = 0UL;
}
- ARRAY_WRITE(rec->regs, rt, read_idreg(idreg) & ~mask);
-
+ rec->regs[rt] = read_idreg(idreg) & ~mask;
return true;
}
@@ -145,16 +145,15 @@
static unsigned long get_sysreg_write_value(struct rec *rec, unsigned long esr)
{
- unsigned int rt = esr_sysreg_rt(esr);
- unsigned long val;
+ /* Rt bits [9:5] of ISS field cannot exceed 0b11111 */
+ unsigned int rt = ESR_EL2_SYSREG_ISS_RT(esr);
/* Handle reads from XZR register */
if (rt == 31U) {
return 0UL;
}
- ARRAY_READ(rec->regs, rt, val);
- return val;
+ return rec->regs[rt];
}
static void emulate_sysreg_access_ns(struct rec *rec, struct rmi_rec_exit *rec_exit,
@@ -175,6 +174,7 @@
/*
* Read Rt value from the issued instruction,
* the general-purpose register used for the transfer.
+ * Rt bits [9:5] of ISS field cannot exceed 0b11111.
*/
unsigned int rt = ESR_EL2_SYSREG_ISS_RT(esr);
unsigned int i;
@@ -202,7 +202,7 @@
* Handle writes to XZR register.
*/
if (!ESR_EL2_SYSREG_IS_WRITE(esr) && (rt != 31U)) {
- ARRAY_WRITE(rec->regs, rt, 0UL);
+ rec->regs[rt] = 0UL;
}
sysreg = esr & ESR_EL2_SYSREG_MASK;
diff --git a/runtime/rmi/run.c b/runtime/rmi/run.c
index 27ec48e..fad297a 100644
--- a/runtime/rmi/run.c
+++ b/runtime/rmi/run.c
@@ -107,7 +107,9 @@
static void complete_sysreg_emulation(struct rec *rec, struct rmi_rec_entry *rec_entry)
{
unsigned long esr = rec->last_run_info.esr;
- unsigned int rt = esr_sysreg_rt(esr);
+
+ /* Rt bits [9:5] of ISS field cannot exceed 0b11111 */
+ unsigned int rt = ESR_EL2_SYSREG_ISS_RT(esr);
if ((esr & ESR_EL2_EC_MASK) != ESR_EL2_EC_SYSREG) {
return;