feat(sve): add SVE support for Realms
This feature adds Scalable Vector Extension (SVE) support for Realms.
* Detect, report and validate SVE flags in RMM feature register 0.
* Emulate read access to ID_AA64PFR0_EL1, ID_AA64ZFR0_EL1_SVE registers
* Support realm creation with SVE flags and variable vector length
* Implement lazy save/restore of SVE context for NS and Realm world.
* Handle both FPU and SVE state context for NS and Realm world.
* Refactor existing SVE helper routines to lib/arch
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie906f9d4a4c40e5acb875cce95c768f752fb0d8a
diff --git a/lib/allocator/include/memory_alloc.h b/lib/allocator/include/memory_alloc.h
index 1ff2b9e..852b648 100644
--- a/lib/allocator/include/memory_alloc.h
+++ b/lib/allocator/include/memory_alloc.h
@@ -17,9 +17,21 @@
/* Number of pages per REC for PMU state */
#define REC_PMU_PAGES 1
+#define REC_PMU_SIZE (REC_PMU_PAGES * SZ_4K)
-/* Number of pages per REC to be allocated */
-#define REC_NUM_PAGES (REC_HEAP_PAGES + REC_PMU_PAGES)
+/*
+ * SIMD context that holds FPU/SVE registers. Space to save max arch supported
+ * SVE vector length of 2048 bits.
+ * Size of 32 Z registers (256 bytes each): 8192 bytes
+ * Size of 16 P registers (32 bytes each) : 512 bytes
+ * Size of 1 FFR register (32 bytes each) : 32 bytes
+ * Size of other status registers : 32 bytes
+ * Total size is ~3 Pages (rounded up to page size).
+ */
+#define REC_SIMD_PAGES 3
+
+/* Number of aux granules pages per REC to be used */
+#define REC_NUM_PAGES (REC_HEAP_PAGES + REC_PMU_PAGES + REC_SIMD_PAGES)
struct buffer_alloc_ctx {
unsigned char *buf;