feat(pmu): add PMU support for Realms
This patch adds support for using PMU in Realms.
It adds 'bool pmu_enabled' and 'unsigned int pmu_num_cnts'
variables in 'struct rd' and 'struct rec.realm_info'.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I13aad600a0215ba66d25be12ede5f4b86e6b018a
diff --git a/runtime/core/sysregs.c b/runtime/core/sysregs.c
index c45b474..940b0b4 100644
--- a/runtime/core/sysregs.c
+++ b/runtime/core/sysregs.c
@@ -36,30 +36,32 @@
* - Debug architecture version:
* set in ID_AA64DFR0_EL1_SET
* - Trace unit System registers not implemented
- * - PMU is not implemented
* - Number of breakpoints:
* set in ID_AA64DFR0_EL1_SET
+ * - PMU Snapshot extension not implemented
* - Number of watchpoints:
* set in ID_AA64DFR0_EL1_SET
+ * - Synchronous-exception-based event profiling not implemented
* - Number of breakpoints that are context-aware
* - Statistical Profiling Extension not implemented
* - Armv8.4 Self-hosted Trace Extension not implemented
* - Trace Buffer Extension not implemented
- * - FEAT_MTPMU not implemented
* - Branch Record Buffer Extension not implemented
+ * - Trace Buffer External Mode not implemented
*/
#define ID_AA64DFR0_EL1_CLEAR \
MASK(ID_AA64DFR0_EL1_DebugVer) | \
MASK(ID_AA64DFR0_EL1_TraceVer) | \
- MASK(ID_AA64DFR0_EL1_PMUVer) | \
MASK(ID_AA64DFR0_EL1_BRPs) | \
+ MASK(ID_AA64DFR0_EL1_PMSS) | \
MASK(ID_AA64DFR0_EL1_WRPs) | \
+ MASK(ID_AA64DFR0_EL1_SEBEP) | \
MASK(ID_AA64DFR0_EL1_CTX_CMPS) | \
MASK(ID_AA64DFR0_EL1_PMSVer) | \
MASK(ID_AA64DFR0_EL1_TraceFilt) | \
MASK(ID_AA64DFR0_EL1_TraceBuffer) | \
- MASK(ID_AA64DFR0_EL1_MTPMU) | \
- MASK(ID_AA64DFR0_EL1_BRBE)
+ MASK(ID_AA64DFR0_EL1_BRBE) | \
+ MASK(ID_AA64DFR0_EL1_ExtTrcBuff)
/*
* Set fields:
@@ -67,12 +69,23 @@
* - Number of breakpoints: 2
* - Number of watchpoints: 2
*/
-#define ID_AA64DFR0_EL1_SET \
- ID_AA64DFR0_EL1_DebugVer_8 | \
- INPLACE(ID_AA64DFR0_EL1_BRPs, 1UL) | \
+#define ID_AA64DFR0_EL1_SET \
+ INPLACE(ID_AA64DFR0_EL1_DebugVer, ID_AA64DFR0_EL1_Debugv8) | \
+ INPLACE(ID_AA64DFR0_EL1_BRPs, 1UL) | \
INPLACE(ID_AA64DFR0_EL1_WRPs, 1UL)
/*
+ * ID_AA64DFR1_EL1:
+ *
+ * Cleared fields:
+ * - Exception-based event profiling not implemented
+ * - PMU fixed-function instruction counter not implemented
+ */
+#define ID_AA64DFR1_EL1_CLEAR \
+ MASK(ID_AA64DFR1_EL1_EBEP) | \
+ MASK(ID_AA64DFR1_EL1_ICNTR)
+
+/*
* ID_AA64ISAR1_EL1:
*
* Cleared fields:
@@ -147,7 +160,7 @@
value = SYSREG_READ_CLEAR_SET(DFR0);
break;
SYSREG_CASE(DFR1)
- value = SYSREG_READ(DFR1);
+ value = SYSREG_READ_CLEAR(DFR1);
break;
SYSREG_CASE(ISAR0)
value = SYSREG_READ(ISAR0);