feat(pmu): add PMU support for Realms
This patch adds support for using PMU in Realms.
It adds 'bool pmu_enabled' and 'unsigned int pmu_num_cnts'
variables in 'struct rd' and 'struct rec.realm_info'.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I13aad600a0215ba66d25be12ede5f4b86e6b018a
diff --git a/lib/arch/include/arch.h b/lib/arch/include/arch.h
index cc46639..6d898fe 100644
--- a/lib/arch/include/arch.h
+++ b/lib/arch/include/arch.h
@@ -395,6 +395,9 @@
#define ID_AA64DFR0_EL1_HPMN0_SHIFT UL(60)
#define ID_AA64DFR0_EL1_HPMN0_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_ExtTrcBuff_SHIFT UL(56)
+#define ID_AA64DFR0_EL1_ExtTrcBuff_WIDTH UL(4)
+
#define ID_AA64DFR0_EL1_BRBE_SHIFT UL(52)
#define ID_AA64DFR0_EL1_BRBE_WIDTH UL(4)
@@ -416,15 +419,26 @@
#define ID_AA64DFR0_EL1_CTX_CMPS_SHIFT UL(28)
#define ID_AA64DFR0_EL1_CTX_CMPS_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_SEBEP_SHIFT UL(24)
+#define ID_AA64DFR0_EL1_SEBEP_WIDTH UL(4)
+
#define ID_AA64DFR0_EL1_WRPs_SHIFT UL(20)
#define ID_AA64DFR0_EL1_WRPs_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_PMSS_SHIFT UL(16)
+#define ID_AA64DFR0_EL1_PMSS_WIDTH UL(4)
+
#define ID_AA64DFR0_EL1_BRPs_SHIFT UL(12)
#define ID_AA64DFR0_EL1_BRPs_WIDTH UL(4)
#define ID_AA64DFR0_EL1_PMUVer_SHIFT UL(8)
#define ID_AA64DFR0_EL1_PMUVer_WIDTH UL(4)
+/* Performance Monitors Extension version */
+#define ID_AA64DFR0_EL1_PMUv3p7 UL(7)
+#define ID_AA64DFR0_EL1_PMUv3p8 UL(8)
+#define ID_AA64DFR0_EL1_PMUv3p9 UL(9)
+
#define ID_AA64DFR0_EL1_TraceVer_SHIFT UL(4)
#define ID_AA64DFR0_EL1_TraceVer_WIDTH UL(4)
@@ -432,11 +446,18 @@
#define ID_AA64DFR0_EL1_DebugVer_WIDTH UL(4)
/* Debug architecture version */
-#define ID_AA64DFR0_EL1_DebugVer_8 UL(6)
-#define ID_AA64DFR0_EL1_DebugVer_8_VHE UL(7)
-#define ID_AA64DFR0_EL1_DebugVer_8_2 UL(8)
-#define ID_AA64DFR0_EL1_DebugVer_8_4 UL(9)
-#define ID_AA64DFR0_EL1_DebugVer_8_8 UL(10)
+#define ID_AA64DFR0_EL1_Debugv8 UL(6)
+#define ID_AA64DFR0_EL1_DebugVHE UL(7)
+#define ID_AA64DFR0_EL1_Debugv8p2 UL(8)
+#define ID_AA64DFR0_EL1_Debugv8p4 UL(9)
+#define ID_AA64DFR0_EL1_Debugv8p8 UL(10)
+
+/* ID_AA64DFR1_EL1 definitions */
+#define ID_AA64DFR1_EL1_EBEP_SHIFT UL(48)
+#define ID_AA64DFR1_EL1_EBEP_WIDTH UL(4)
+
+#define ID_AA64DFR1_EL1_ICNTR_SHIFT UL(36)
+#define ID_AA64DFR1_EL1_ICNTR_WIDTH UL(4)
/* ID_AA64PFR0_EL1 definitions */
#define ID_AA64PFR0_EL1_SVE_SHIFT UL(32)
@@ -463,34 +484,35 @@
#define ID_AA64MMFR0_EL1_ECV_SHIFT UL(60)
#define ID_AA64MMFR0_EL1_ECV_WIDTH UL(4)
-#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
+#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED UL(0x0)
+#define ID_AA64MMFR0_EL1_ECV_SUPPORTED UL(0x1)
#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
#define ID_AA64MMFR0_EL1_FGT_SHIFT UL(56)
#define ID_AA64MMFR0_EL1_FGT_WIDTH UL(4)
-#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED UL(0x0)
+#define ID_AA64MMFR0_EL1_FGT_SUPPORTED UL(0x1)
+#define ID_AA64MMFR0_EL1_FGT2_SUPPORTED UL(0x2)
#define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT U(40)
#define ID_AA64MMFR0_EL1_TGRAN4_2_WIDTH U(4)
-#define ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4 ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN4_2_NOT_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED ULL(0x2)
-#define ID_AA64MMFR0_EL1_TGRAN4_2_LPA2 ULL(0x3)
+#define ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4 UL(0x0)
+#define ID_AA64MMFR0_EL1_TGRAN4_2_NOT_SUPPORTED UL(0x1)
+#define ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED UL(0x2)
+#define ID_AA64MMFR0_EL1_TGRAN4_2_LPA2 UL(0x3)
#define ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT UL(32)
#define ID_AA64MMFR0_EL1_TGRAN16_2_WIDTH UL(4)
-#define ID_AA64MMFR0_EL1_TGRAN16_2_TGRAN16 ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN16_2_NOT_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED ULL(0x2)
-#define ID_AA64MMFR0_EL1_TGRAN16_2_LPA2 ULL(0x3)
+#define ID_AA64MMFR0_EL1_TGRAN16_2_TGRAN16 UL(0x0)
+#define ID_AA64MMFR0_EL1_TGRAN16_2_NOT_SUPPORTED UL(0x1)
+#define ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED UL(0x2)
+#define ID_AA64MMFR0_EL1_TGRAN16_2_LPA2 UL(0x3)
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT UL(28)
#define ID_AA64MMFR0_EL1_TGRAN4_WIDTH UL(4)
-#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ULL(0x1)
-#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
+#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED UL(0x0)
+#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 UL(0x1)
+#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED UL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT UL(24)
#define ID_AA64MMFR0_EL1_TGRAN64_WIDTH UL(4)
@@ -627,10 +649,17 @@
SCTLR_EL1_SA0 | SCTLR_EL1_SA)
/* PMCR_EL0 Definitions */
-#define PMCR_EL0_LC_BIT (UL(1) << 6)
+#define PMCR_EL0_N_SHIFT 11
+#define PMCR_EL0_N_WIDTH 5
+#define PMCR_EL0_LC_BIT (UL(1) << 6)
+#define PMCR_EL0_DP_BIT (UL(1) << 5)
+#define PMCR_EL0_C_BIT (UL(1) << 2)
+#define PMCR_EL0_P_BIT (UL(1) << 1)
+#define PMCR_EL0_E_BIT (UL(1) << 0)
-#define PMCR_EL0_RES1 PMCR_EL0_LC_BIT
-
+#define PMCR_EL0_INIT (PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT)
+#define PMCR_EL0_INIT_RESET (PMCR_EL0_INIT | PMCR_EL0_C_BIT | \
+ PMCR_EL0_P_BIT)
/* MDSCR_EL1 Definitions */
#define MDSCR_EL1_TDCC_BIT (UL(1) << 12)
@@ -721,6 +750,10 @@
CPTR_EL2_RES1)
/* MDCR_EL2 definitions */
+#define MDCR_EL2_HPMFZS (UL(1) << 36)
+#define MDCR_EL2_HPMFZO (UL(1) << 29)
+#define MDCR_EL2_MTPME (UL(1) << 28)
+#define MDCR_EL2_TDCC (UL(1) << 27)
#define MDCR_EL2_HLP (UL(1) << 26)
#define MDCR_EL2_HCCD (UL(1) << 23)
#define MDCR_EL2_TTRF (UL(1) << 19)
@@ -735,9 +768,16 @@
#define MDCR_EL2_HPME_BIT (UL(1) << 7)
#define MDCR_EL2_TPM_BIT (UL(1) << 6)
#define MDCR_EL2_TPMCR_BIT (UL(1) << 5)
-#define MDCR_EL2_INIT (MDCR_EL2_TPMCR_BIT \
- | MDCR_EL2_TPM_BIT \
- | MDCR_EL2_TDA_BIT)
+
+#define MDCR_EL2_HPMN_SHIFT UL(0)
+#define MDCR_EL2_HPMN_WIDTH UL(5)
+
+#define MDCR_EL2_INIT (MDCR_EL2_MTPME | \
+ MDCR_EL2_HCCD | \
+ MDCR_EL2_HPMD | \
+ MDCR_EL2_TDA_BIT | \
+ MDCR_EL2_TPM_BIT | \
+ MDCR_EL2_TPMCR_BIT)
/* MPIDR definitions */
#define MPIDR_EL1_AFF_MASK 0xFF