feat(drivers): Enable Generic PL011 UART config
This patch adds a config build option PL011_GENERIC_SBSA_UART to build
PL011 driver as Generic SBSA compliant peripheral. This option is
typically enabled in hardware validation environments.
Change-Id: Icb17c0612c9e936712ba713d53948c2460731177
Signed-off-by: Jacob Man Chun Yiu <jacobmanchun.yiu@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 0fa4a77..b111e1f 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -277,6 +277,7 @@
RMM_TOOLCHAIN ,gnu | llvm , ,"Toolchain name"
LOG_LEVEL ,0 - 50 ,40(Debug) 20(Release) ,"Log level to apply for RMM (0 - 50)."
RMM_STATIC_ANALYSIS , , ,"Enable static analysis checkers"
+ PL011_GENERIC_SBSA_UART ,ON | OFF ,OFF ,"Enable Generic (SBSA Compliant) PL011. This a subset of PL011 UART"
PLAT_CMN_CTX_MAX_XLAT_TABLES , ,0 ,"Maximum number of translation tables used by the runtime context"
PLAT_CMN_EXTRA_MMAP_REGIONS , ,0 ,"Extra platform mmap regions that need to be mapped in S1 xlat tables"
PLAT_CMN_VIRT_ADDR_SPACE_WIDTH, ,38 ,"Stage 1 Virtual address space width in bits for this platform"
diff --git a/drivers/pl011/CMakeLists.txt b/drivers/pl011/CMakeLists.txt
index 0b29206..4262839 100644
--- a/drivers/pl011/CMakeLists.txt
+++ b/drivers/pl011/CMakeLists.txt
@@ -3,11 +3,26 @@
# SPDX-FileCopyrightText: Copyright TF-RMM Contributors.
#
+#
+# Option to make PL011 SBSA compliant. Typically only enabled in
+# hardware validation environments.
+#
+arm_config_option(
+ NAME PL011_GENERIC_SBSA_UART
+ HELP "Enable Generic (SBSA Compliant) PL011. This a subset of PL011 UART"
+ STRINGS "ON" "OFF"
+ DEFAULT "OFF")
+
add_library(rmm-driver-pl011)
target_link_libraries(rmm-driver-pl011
PRIVATE rmm-lib)
+if(PL011_GENERIC_SBSA_UART)
+ target_compile_definitions(rmm-driver-pl011
+ PUBLIC "PL011_GENERIC_SBSA_UART=1")
+endif()
+
target_include_directories(rmm-driver-pl011
PUBLIC "include")
diff --git a/drivers/pl011/src/pl011.c b/drivers/pl011/src/pl011.c
index e7137bd..524286b 100644
--- a/drivers/pl011/src/pl011.c
+++ b/drivers/pl011/src/pl011.c
@@ -15,17 +15,18 @@
#define UARTECR 0x04U
#define UARTFR 0x18U
+/* Transmit FIFO full */
+#define PL011_UARTFR_TXFF (U(1) << 5)
+
+#ifndef PL011_GENERIC_SBSA_UART
+
/* PL011 registers (out of the SBSA specification) */
#define UARTIBRD 0x24U
#define UARTFBRD 0x28U
#define UARTLCR_H 0x2CU
#define UARTCR 0x30U
-
/* Flag reg bits */
-/* Transmit FIFO full */
-#define PL011_UARTFR_TXFF (U(1) << 5)
-
/* Control reg bits */
#define PL011_UARTCR_RXE (U(1) << 9) /* Receive enable */
#define PL011_UARTCR_TXE (U(1) << 8) /* Transmit enable */
@@ -38,6 +39,8 @@
#define PL011_UARTLCR_H_WLEN_8 (U(3) << 5)
#define PL011_UARTLCR_H_FEN (U(1) << 4) /* FIFOs Enable */
+#endif /* PL011_GENERIC_SBSA_UART */
+
static inline void pl011_wait(uintptr_t base)
{
/* Wait until there is room in the Tx FIFO */
@@ -78,13 +81,13 @@
unsigned int uart_clk,
unsigned int baud_rate)
{
- unsigned int div;
-
/* Check Base address, baud rate and UART clock for sanity */
if ((base_addr == 0UL) || (uart_clk == 0U) ||
(baud_rate == 0U)) {
return -EINVAL;
}
+#ifndef PL011_GENERIC_SBSA_UART
+ unsigned int div;
/* Disable UART before programming */
write32(0U, (void *)(base_addr + UARTCR));
@@ -100,13 +103,16 @@
/* Enable FIFO and set word length, parity and number of stop bits */
write32(PL011_LINE_CONTROL, (void *)((base_addr) + UARTLCR_H));
+#endif /* PL011_GENERIC_SBSA_UART */
/* Clear any pending errors */
write32(0U, (void *)((base_addr) + UARTECR));
+#ifndef PL011_GENERIC_SBSA_UART
/* Enable Tx, Rx, and UART overall */
write32(PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN,
(void *)((base_addr) + UARTCR));
+#endif /* PL011_GENERIC_SBSA_UART */
pl011_csl.base = base_addr;