fix(unittests): make xlat table tests run for LPA2 and non LPA2 cases
This patch refactors all the xlat lib unittests so they can run
twice, once with FEAT_LPA2 supported and once with that feature
unsupported.
This patch also fixes a small bug on the xlat library in which
the minimum level for a block descriptor was wrongly calculated
when creating translation tables.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I12ae5fc471733135b5bfe60cd71ab1b403a846fd
diff --git a/lib/xlat/include/xlat_defs.h b/lib/xlat/include/xlat_defs.h
index e62bdec..770a665 100644
--- a/lib/xlat/include/xlat_defs.h
+++ b/lib/xlat/include/xlat_defs.h
@@ -81,16 +81,13 @@
(((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
/*
- * In AArch64 state, the MMU may support 4KB, 16KB and 64KB page
- * granularity. For 4KB granularity (the only one supported by
- * this library), a level -1 table descriptor doesn't support
- * block translation. See section Table D8-9 of the ARMv8-A Architecture
- * Reference Manual (Issue I.a) for more information.
- *
- * The define below specifies the first table level that allows block
- * descriptors.
+ * Minimum table level supported by the architecture when FEAT_LPA2 is present.
+ * Since the library is in charge of calculating the minimum level when creating
+ * the translation tables, due to presence of checks for VA size and PA size,
+ * the library would not create a table at level -1 on a non LPA2 system.
+ * Hence there is no need to differentiate the value of this macro for non
+ * LPA2 case.
*/
-#define MIN_LVL_BLOCK_DESC (0)
#define XLAT_TABLE_LEVEL_MIN (-1)
/* Mask used to know if an address belongs to a high va region. */
diff --git a/lib/xlat/include/xlat_tables.h b/lib/xlat/include/xlat_tables.h
index 047e21b..4319bf3 100644
--- a/lib/xlat/include/xlat_tables.h
+++ b/lib/xlat/include/xlat_tables.h
@@ -25,6 +25,14 @@
#ifndef __ASSEMBLER__
/*
+ * The define below specifies the first table level that allows block
+ * descriptors.
+ */
+#define XLAT_MIN_BLOCK_LVL() \
+ ((is_feat_lpa2_4k_present() == true) ? \
+ XLAT_TABLE_LEVEL_MIN + 1U : XLAT_TABLE_LEVEL_MIN + 2U)
+
+/*
* Default granularity size for a struct xlat_mmap_region.
* Useful when no specific granularity is required.
*
@@ -32,7 +40,8 @@
* architectural state and granule size in order to minimize the number of page
* tables required for the mapping.
*/
-#define REGION_DEFAULT_GRANULARITY XLAT_BLOCK_SIZE(MIN_LVL_BLOCK_DESC)
+#define REGION_DEFAULT_GRANULARITY \
+ XLAT_BLOCK_SIZE(XLAT_MIN_BLOCK_LVL())
/*
* Helper macro to define a struct xlat_mmap_region. This macro allows to
diff --git a/lib/xlat/src/xlat_tables_core.c b/lib/xlat/src/xlat_tables_core.c
index cd3039d..162f1ee 100644
--- a/lib/xlat/src/xlat_tables_core.c
+++ b/lib/xlat/src/xlat_tables_core.c
@@ -159,7 +159,7 @@
* descriptors. If not, create a table instead.
*/
if (((dest_pa & XLAT_BLOCK_MASK(level)) != 0U)
- || (level < MIN_LVL_BLOCK_DESC) ||
+ || (level < XLAT_MIN_BLOCK_LVL()) ||
(mm->granularity < XLAT_BLOCK_SIZE(level))) {
return ACTION_CREATE_NEW_TABLE;
} else {
diff --git a/lib/xlat/tests/CMakeLists.txt b/lib/xlat/tests/CMakeLists.txt
index 299aca9..e1e4498 100644
--- a/lib/xlat/tests/CMakeLists.txt
+++ b/lib/xlat/tests/CMakeLists.txt
@@ -3,20 +3,25 @@
# SPDX-FileCopyrightText: Copyright TF-RMM Contributors.
#
-target_include_directories(rmm-lib-xlat
- PRIVATE "tests")
+if(RMM_UNITTESTS)
+ target_include_directories(rmm-lib-xlat
+ PRIVATE "tests")
+
+ target_sources(rmm-lib-xlat
+ PRIVATE "tests/xlat_tests_base_g1.cpp"
+ "tests/xlat_tests_base_g2.cpp"
+ "tests/xlat_test_helpers.c")
+endif()
# Add test functionality
-rmm_build_unittest(NAME xlat_tests_G1
+rmm_build_unittest(NAME xlat_tests_LPA2
LIBRARIES rmm-platform
TARGET rmm-lib-xlat
- SOURCES "tests/xlat_tests_g1.cpp"
- "tests/xlat_test_helpers.c"
+ SOURCES "tests/xlat_tests_lpa2.cpp"
ITERATIONS 10)
-rmm_build_unittest(NAME xlat_tests_G2
+rmm_build_unittest(NAME xlat_tests_no_LPA2
LIBRARIES rmm-platform
TARGET rmm-lib-xlat
- SOURCES "tests/xlat_tests_g2.cpp"
- "tests/xlat_test_helpers.c"
+ SOURCES "tests/xlat_tests_no_lpa2.cpp"
ITERATIONS 10)
diff --git a/lib/xlat/tests/xlat_test_defs.h b/lib/xlat/tests/xlat_test_defs.h
index c36560d..45e6cf6 100644
--- a/lib/xlat/tests/xlat_test_defs.h
+++ b/lib/xlat/tests/xlat_test_defs.h
@@ -8,6 +8,7 @@
#include <utils_def.h>
#include <xlat_defs_private.h>
+#include <xlat_tables.h>
/*
* All the definitions on this file are as per Issue G.a of the
@@ -40,11 +41,12 @@
/*
* The xlat library only supports 4KB of granularity so the lowest level
- * table descriptor that support block translation is Level 1.
- * The following macro specifies the biggest block size that can be
- * mapped by the xlat library.
+ * table descriptor that support block translation is Level 1 (or 0 if
+ * FEAT_LPA2 is supported). The following macro specifies the biggest
+ * block size that can be mapped by the xlat library.
*/
-#define XLAT_TESTS_MAX_BLOCK_SIZE XLAT_BLOCK_SIZE(MIN_LVL_BLOCK_DESC)
+#define XLAT_TESTS_MAX_BLOCK_SIZE \
+ XLAT_BLOCK_SIZE(XLAT_MIN_BLOCK_LVL())
#define XLAT_TESTS_IS_DESC(tte, desc) \
(((tte) & (DESC_MASK)) == (desc))
diff --git a/lib/xlat/tests/xlat_test_helpers.c b/lib/xlat/tests/xlat_test_helpers.c
index c15cdf9..87a2b16 100644
--- a/lib/xlat/tests/xlat_test_helpers.c
+++ b/lib/xlat/tests/xlat_test_helpers.c
@@ -22,6 +22,54 @@
static uint64_t xlat_tables[XLAT_TABLE_ENTRIES * XLAT_TESTS_MAX_TABLES]
__aligned(XLAT_TABLE_SIZE);
+/*
+ * Helper function to perform any system register initialization
+ * needed for the tests.
+ */
+static void xlat_test_helpers_arch_init(bool lpa2_en)
+{
+ unsigned int retval __unused;
+ uint64_t id_aa64mmfr0_el0 = INPLACE(ID_AA64MMFR0_EL1_TGRAN4_2,
+ ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4);
+
+ /* Enable the platform with support for multiple PEs */
+ test_helpers_rmm_start(true);
+
+ /*
+ * Reset the sysreg state so that we can setup
+ * custom values for the tests
+ */
+ host_util_zero_sysregs_and_cbs();
+
+ /* Setup id_aa64mmfr0_el1 */
+ if (lpa2_en == true) {
+ id_aa64mmfr0_el0 |= INPLACE(ID_AA64MMFR0_EL1_PARANGE, 6UL) |
+ INPLACE(ID_AA64MMFR0_EL1_TGRAN4,
+ ID_AA64MMFR0_EL1_TGRAN4_LPA2);
+ } else {
+ id_aa64mmfr0_el0 |= INPLACE(ID_AA64MMFR0_EL1_PARANGE, 5UL) |
+ INPLACE(ID_AA64MMFR0_EL1_TGRAN4,
+ ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED);
+ }
+
+ retval = host_util_set_default_sysreg_cb("id_aa64mmfr0_el1",
+ id_aa64mmfr0_el0);
+
+ /* Initialize MMU registers to 0 */
+ retval = host_util_set_default_sysreg_cb("sctlr_el2", 0UL);
+ retval = host_util_set_default_sysreg_cb("mair_el2", 0UL);
+ retval = host_util_set_default_sysreg_cb("tcr_el2", 0UL);
+ retval = host_util_set_default_sysreg_cb("ttbr0_el2", 0UL);
+ retval = host_util_set_default_sysreg_cb("ttbr1_el2", 0UL);
+
+ assert(retval == 0);
+
+ /* Make sure current cpu id is 0 (primary processor) */
+ host_util_set_cpuid(0U);
+
+ test_helpers_expect_assert_fail(false);
+}
+
void xlat_test_helpers_init_ctx_tbls(struct xlat_ctx_tbls *ctx_tbls,
uint64_t *tbls,
unsigned int tables_num,
@@ -64,43 +112,10 @@
ctx->tbls = tbls;
}
-void xlat_test_hepers_arch_init(void)
+void xlat_test_setup(bool lpa2)
{
- unsigned int retval __unused;
-
- /* Enable the platform with support for multiple PEs */
- test_helpers_rmm_start(true);
-
- /*
- * Reset the sysreg state so that we can setup
- * custom values for the tests
- */
- host_util_zero_sysregs_and_cbs();
-
- /*
- * Setup id_aa64mmfr0_el1 with a PA size of 52 bits
- * and 4K granularity with 52 bits support on stage 1 and 2.
- */
- retval = host_util_set_default_sysreg_cb("id_aa64mmfr0_el1",
- INPLACE(ID_AA64MMFR0_EL1_PARANGE, 6UL) |
- INPLACE(ID_AA64MMFR0_EL1_TGRAN4,
- ID_AA64MMFR0_EL1_TGRAN4_LPA2) |
- INPLACE(ID_AA64MMFR0_EL1_TGRAN4_2,
- ID_AA64MMFR0_EL1_TGRAN4_2_TGRAN4));
-
- /* Initialize MMU registers to 0 */
- retval = host_util_set_default_sysreg_cb("sctlr_el2", 0UL);
- retval = host_util_set_default_sysreg_cb("mair_el2", 0UL);
- retval = host_util_set_default_sysreg_cb("tcr_el2", 0UL);
- retval = host_util_set_default_sysreg_cb("ttbr0_el2", 0UL);
- retval = host_util_set_default_sysreg_cb("ttbr1_el2", 0UL);
-
- assert(retval == 0);
-
- /* Make sure current cpu id is 0 (primary processor) */
- host_util_set_cpuid(0U);
-
- test_helpers_expect_assert_fail(false);
+ test_helpers_init();
+ xlat_test_helpers_arch_init(lpa2);
}
void xlat_test_helpers_set_parange(unsigned int parange)
diff --git a/lib/xlat/tests/xlat_test_helpers.h b/lib/xlat/tests/xlat_test_helpers.h
index 73229a6..bcbea5c 100644
--- a/lib/xlat/tests/xlat_test_helpers.h
+++ b/lib/xlat/tests/xlat_test_helpers.h
@@ -16,6 +16,10 @@
/* Maximum number of mmap regions to use for tests */
#define XLAT_TESTS_MAX_MMAPS (20U)
+/* Macros to specify LPA2 status */
+#define LPA2_ENABLED (true)
+#define LPA2_DISABLED (false)
+
/*
* Return the minimum lookup level supported.
*/
@@ -80,12 +84,6 @@
struct xlat_ctx_cfg *cfg,
struct xlat_ctx_tbls *tbls);
-/*
- * Helper function to perform any system register initialization
- * needed for the tests.
- */
-void xlat_test_hepers_arch_init(void);
-
/* Helper function to return a random set of attributes for a mmap region */
uint64_t xlat_test_helpers_rand_mmap_attrs(void);
@@ -150,4 +148,10 @@
*/
void xlat_test_helpers_set_parange(unsigned int parange);
+/*
+ * Function to setup the environment for the tests specifying
+ * whether FEAT_LPA2 is supported or not.
+ */
+void xlat_test_setup(bool lpa2);
+
#endif /* XLAT_TEST_HELPERS_H */
diff --git a/lib/xlat/tests/xlat_tests_base.h b/lib/xlat/tests/xlat_tests_base.h
new file mode 100644
index 0000000..c16218f
--- /dev/null
+++ b/lib/xlat/tests/xlat_tests_base.h
@@ -0,0 +1,66 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: Copyright TF-RMM Contributors.
+ */
+
+#ifndef XLAT_TESTS_BASE
+#define XLAT_TESTS_BASE
+
+void map_region_full_spec_tc1(void);
+void map_region_tc1(void);
+void map_region_flat_tc1(void);
+void map_region_transient_tc1(void);
+
+void xlat_ctx_cfg_init_tc1(void);
+void xlat_ctx_cfg_init_tc2(void);
+void xlat_ctx_cfg_init_tc3(void);
+void xlat_ctx_cfg_init_tc4(void);
+void xlat_ctx_cfg_init_tc5(void);
+void xlat_ctx_cfg_init_tc6(void);
+void xlat_ctx_cfg_init_tc7(void);
+void xlat_ctx_cfg_init_tc8(void);
+void xlat_ctx_cfg_init_tc9(void);
+void xlat_ctx_cfg_init_tc10(void);
+void xlat_ctx_cfg_init_tc11(void);
+void xlat_ctx_cfg_init_tc12(void);
+void xlat_ctx_cfg_init_tc13(void);
+
+void xlat_ctx_init_tc1(void);
+void xlat_ctx_init_tc2(void);
+void xlat_ctx_init_tc3(void);
+void xlat_ctx_init_tc4(void);
+void xlat_ctx_init_tc5(void);
+void xlat_ctx_init_tc6(void);
+
+void xlat_get_llt_from_va_tc1(void);
+void xlat_get_llt_from_va_tc2(void);
+void xlat_get_llt_from_va_tc3(void);
+void xlat_get_llt_from_va_tc4(void);
+void xlat_get_llt_from_va_tc5(void);
+void xlat_get_llt_from_va_tc6(void);
+void xlat_get_llt_from_va_tc7(void);
+void xlat_get_llt_from_va_tc8(void);
+void xlat_get_llt_from_va_tc9(void);
+
+void xlat_get_tte_ptr_tc1(void);
+void xlat_get_tte_ptr_tc2(void);
+void xlat_get_tte_ptr_tc3(void);
+void xlat_get_tte_ptr_tc4(void);
+
+void xlat_unmap_memory_page_tc1(void);
+void xlat_unmap_memory_page_tc2(void);
+void xlat_unmap_memory_page_tc3(void);
+
+void xlat_map_memory_page_with_attrs_tc1(void);
+void xlat_map_memory_page_with_attrs_tc2(void);
+void xlat_map_memory_page_with_attrs_tc3(void);
+
+void xlat_arch_setup_mmu_cfg_tc1(void);
+void xlat_arch_setup_mmu_cfg_tc2(void);
+void xlat_arch_setup_mmu_cfg_tc3(void);
+void xlat_arch_setup_mmu_cfg_tc4(void);
+void xlat_arch_setup_mmu_cfg_tc5(void);
+
+void xlat_get_oa_from_tte_tc1(void);
+
+#endif /* XLAT_TESTS_BASE */
diff --git a/lib/xlat/tests/xlat_tests_g1.cpp b/lib/xlat/tests/xlat_tests_base_g1.cpp
similarity index 94%
rename from lib/xlat/tests/xlat_tests_g1.cpp
rename to lib/xlat/tests/xlat_tests_base_g1.cpp
index 7eb2b6c..19893b5 100644
--- a/lib/xlat/tests/xlat_tests_g1.cpp
+++ b/lib/xlat/tests/xlat_tests_base_g1.cpp
@@ -131,18 +131,7 @@
region, init_mmap, mmaps, true);
}
-TEST_GROUP(xlat_tests_G1) {
- TEST_SETUP()
- {
- test_helpers_init();
- xlat_test_hepers_arch_init();
- }
-
- TEST_TEARDOWN()
- {}
-};
-
-TEST(xlat_tests_G1, MAP_REGION_FULL_SPEC_TC1)
+void map_region_full_spec_tc1(void)
{
/***************************************************************
* TEST CASE 1:
@@ -172,7 +161,7 @@
sizeof(struct xlat_mmap_region));
}
-TEST(xlat_tests_G1, MAP_REGION_TC1)
+void map_region_tc1(void)
{
/***************************************************************
* TEST CASE 1:
@@ -206,7 +195,7 @@
sizeof(struct xlat_mmap_region));
}
-TEST(xlat_tests_G1, MAP_REGION_FLAT_TC1)
+void map_region_flat_tc1(void)
{
/***************************************************************
* TEST CASE 1:
@@ -242,7 +231,7 @@
sizeof(struct xlat_mmap_region));
}
-TEST(xlat_tests_G1, MAP_REGION_TRANSIENT_TC1)
+void map_region_transient_tc1(void)
{
/***************************************************************
* TEST CASE 1:
@@ -282,7 +271,7 @@
sizeof(struct xlat_mmap_region));
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC1)
+void xlat_ctx_cfg_init_tc1(void)
{
struct xlat_ctx_cfg expected_cfg, test_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -334,7 +323,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC2)
+void xlat_ctx_cfg_init_tc2(void)
{
struct xlat_ctx_cfg foo_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -369,7 +358,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC3)
+void xlat_ctx_cfg_init_tc3(void)
{
struct xlat_ctx_cfg test_cfg;
xlat_addr_region_id_t region;
@@ -399,7 +388,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC4)
+void xlat_ctx_cfg_init_tc4(void)
{
struct xlat_ctx_cfg foo_cfg, test_cfg;
struct xlat_mmap_region test_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -438,7 +427,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC5)
+void xlat_ctx_cfg_init_tc5(void)
{
struct xlat_ctx_cfg test_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -469,7 +458,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC6)
+void xlat_ctx_cfg_init_tc6(void)
{
struct xlat_ctx_cfg test_cfg, foo_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -551,7 +540,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC7)
+void xlat_ctx_cfg_init_tc7(void)
{
struct xlat_ctx_cfg test_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -587,7 +576,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC8)
+void xlat_ctx_cfg_init_tc8(void)
{
struct xlat_ctx_cfg test_cfg, foo_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -748,7 +737,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC9)
+void xlat_ctx_cfg_init_tc9(void)
{
struct xlat_ctx_cfg test_cfg, foo_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -834,7 +823,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC10)
+void xlat_ctx_cfg_init_tc10(void)
{
struct xlat_ctx_cfg test_cfg, foo_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -881,7 +870,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC11)
+void xlat_ctx_cfg_init_tc11(void)
{
struct xlat_ctx_cfg test_cfg, foo_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -929,7 +918,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_cfg_init_TC12)
+void xlat_ctx_cfg_init_tc12(void)
{
struct xlat_ctx_cfg test_cfg, foo_cfg;
struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
@@ -972,7 +961,54 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_init_TC1)
+void xlat_ctx_cfg_init_tc13(void)
+{
+ struct xlat_ctx_cfg expected_cfg, test_cfg;
+ struct xlat_mmap_region init_mmap[XLAT_TESTS_MAX_MMAPS];
+ struct xlat_mmap_region val_mmap[XLAT_TESTS_MAX_MMAPS];
+ xlat_addr_region_id_t region;
+ int retval;
+ uint64_t max_va_size = XLAT_TEST_MAX_VA_SIZE();
+
+ /***************************************************************
+ * TEST CASE 13:
+ *
+ * Running without support for FEAT_LPA2, initialize a
+ * xlat_ctx_cfg structure with random data through
+ * xlat_ctx_cfg_init() but forcing to use a granularity for
+ * level -1 (only supported for FEAT_LPA2). Then verify that the
+ * initialization fails as expected.
+ *
+ * Note: This test is only supported for non-LPA2 runs.
+ ***************************************************************/
+
+ /* Ensure FEAT_LPA2 is not supported */
+ CHECK_FALSE(is_feat_lpa2_4k_present());
+
+ for (unsigned int i = 0U; i < (unsigned int)VA_REGIONS; i++) {
+ region = (xlat_addr_region_id_t)i;
+
+ /* Clean the data structures */
+ memset((void *)&test_cfg, 0, sizeof(struct xlat_ctx_cfg));
+
+ /* Initialize the test structures with the expected values */
+ xlat_test_cfg_init_setup(&expected_cfg, &init_mmap[0],
+ &val_mmap[0], XLAT_TESTS_MAX_MMAPS,
+ max_va_size, region);
+
+ /* Force an incorrect granularity */
+ init_mmap[0].granularity = XLAT_BLOCK_SIZE(-1);
+
+ /* Initialize the test structure */
+ retval = xlat_ctx_cfg_init(&test_cfg, region, &init_mmap[0],
+ 1U, max_va_size);
+
+ /* Verify the result */
+ CHECK_TRUE(retval == -EINVAL);
+ }
+}
+
+void xlat_ctx_init_tc1(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg, val_cfg;
@@ -1050,7 +1086,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_init_TC2)
+void xlat_ctx_init_tc2(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1085,7 +1121,7 @@
CHECK_TRUE(retval == -EINVAL);
}
-TEST(xlat_tests_G1, xlat_ctx_init_TC3)
+void xlat_ctx_init_tc3(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1177,7 +1213,7 @@
}
}
-ASSERT_TEST(xlat_tests_G1, xlat_ctx_init_TC4)
+void xlat_ctx_init_tc4(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1233,7 +1269,7 @@
}
}
-TEST(xlat_tests_G1, xlat_ctx_init_TC5)
+void xlat_ctx_init_tc5(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
diff --git a/lib/xlat/tests/xlat_tests_g2.cpp b/lib/xlat/tests/xlat_tests_base_g2.cpp
similarity index 95%
rename from lib/xlat/tests/xlat_tests_g2.cpp
rename to lib/xlat/tests/xlat_tests_base_g2.cpp
index 8d218a8..c25c26e 100644
--- a/lib/xlat/tests/xlat_tests_g2.cpp
+++ b/lib/xlat/tests/xlat_tests_base_g2.cpp
@@ -22,17 +22,6 @@
#include <xlat_test_helpers.h>
}
-TEST_GROUP(xlat_tests_G2) {
- TEST_SETUP()
- {
- test_helpers_init();
- xlat_test_hepers_arch_init();
- }
-
- TEST_TEARDOWN()
- {}
-};
-
/*
* Generate VA space parameters given a walk start level and a region.
* The VA returned will fit in a single table of level `level`, so that
@@ -284,7 +273,7 @@
}
}
-TEST(xlat_tests_G2, xlat_ctx_init_TC6)
+void xlat_ctx_init_tc6(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -302,8 +291,9 @@
* TEST CASE 6:
*
* For each possible base level, create a set of mmap regions
- * ranging from level 1 (lowest level at which a valid walk can
- * finish) to XLAT_TABLE_LEVEL_MAX.
+ * ranging from level 1 or 0 (lowest level at which a valid walk can
+ * finish depending on whether FEAT_LPA2 is available) to
+ * XLAT_TABLE_LEVEL_MAX.
*
* For each possible (va_region, base_lvl, end_lvl) triplet for a
* base table there will be three mmap regions created:
@@ -328,8 +318,8 @@
mmap_count = 3U;
- /* The first level that supports blocks is L1 */
- for (end_lvl = 1U; end_lvl <= XLAT_TABLE_LEVEL_MAX; end_lvl++) {
+ end_lvl = XLAT_MIN_BLOCK_LVL();
+ for (; end_lvl <= XLAT_TABLE_LEVEL_MAX; end_lvl++) {
for (int i = 0U; i < VA_REGIONS; i++) {
va_region = (xlat_addr_region_id_t)i;
@@ -389,7 +379,7 @@
}
}
-TEST(xlat_tests_G2, xlat_get_llt_from_va_TC1)
+void xlat_get_llt_from_va_tc1(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -411,8 +401,9 @@
* TEST CASE 1:
*
* For each possible base level, create a set of mmap regions
- * ranging from level 1 (lowest level at which a valid walk can
- * finish) to XLAT_TABLE_LEVEL_MAX.
+ * ranging from level 1 or 0 (lowest level at which a valid walk
+ * can finish depending on whether FEAT_LPA2 is available) to
+ * XLAT_TABLE_LEVEL_MAX.
*
* For each possible (va_region, base_lvl, end_lvl) triplet,
* create 3 mappings that will correspond to a tte in the Last
@@ -425,9 +416,8 @@
va_region = (xlat_addr_region_id_t)test_helpers_get_rand_in_range(
0, VA_REGIONS - 1);
- for (end_lvl = 1U;
- end_lvl <= XLAT_TABLE_LEVEL_MAX;
- end_lvl++) {
+ end_lvl = XLAT_MIN_BLOCK_LVL();
+ for (; end_lvl <= XLAT_TABLE_LEVEL_MAX; end_lvl++) {
for (base_lvl = XLAT_TEST_MIN_LVL();
base_lvl <= end_lvl;
@@ -536,7 +526,7 @@
}
}
-TEST(xlat_tests_G2, xlat_get_llt_from_va_TC2)
+void xlat_get_llt_from_va_tc2(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -644,7 +634,7 @@
}
}
-TEST(xlat_tests_G2, xlat_get_llt_from_va_TC3)
+void xlat_get_llt_from_va_tc3(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -764,7 +754,7 @@
XLAT_TESTS_MAX_TABLES);
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_llt_from_va_TC4)
+void xlat_get_llt_from_va_tc4(void)
{
struct xlat_ctx ctx;
@@ -790,7 +780,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_llt_from_va_TC5)
+void xlat_get_llt_from_va_tc5(void)
{
struct xlat_llt_info tbl_info;
@@ -810,7 +800,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_llt_from_va_TC6)
+void xlat_get_llt_from_va_tc6(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -838,7 +828,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_llt_from_va_TC7)
+void xlat_get_llt_from_va_tc7(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -866,7 +856,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_llt_from_va_TC8)
+void xlat_get_llt_from_va_tc8(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -898,7 +888,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_llt_from_va_TC9)
+void xlat_get_llt_from_va_tc9(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -930,7 +920,7 @@
test_helpers_fail_if_no_assert_failed();
}
-TEST(xlat_tests_G2, xlat_get_tte_ptr_TC1)
+void xlat_get_tte_ptr_tc1(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1112,7 +1102,7 @@
}
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_tte_ptr_TC2)
+void xlat_get_tte_ptr_tc2(void)
{
/***************************************************************
* TEST CASE 2:
@@ -1126,7 +1116,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_tte_ptr_TC3)
+void xlat_get_tte_ptr_tc3(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1155,7 +1145,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_get_tte_ptr_TC4)
+void xlat_get_tte_ptr_tc4(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1184,7 +1174,7 @@
test_helpers_fail_if_no_assert_failed();
}
-TEST(xlat_tests_G2, xlat_unmap_memory_page_TC1)
+void xlat_unmap_memory_page_tc1(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1221,8 +1211,8 @@
mmap_count = 3;
base_lvl = XLAT_TEST_MIN_LVL();
- /* The first look-up level that supports blocks is L1 */
- for (end_lvl = 1; end_lvl <= XLAT_TABLE_LEVEL_MAX; end_lvl++) {
+ end_lvl = XLAT_MIN_BLOCK_LVL();
+ for (; end_lvl <= XLAT_TABLE_LEVEL_MAX; end_lvl++) {
for (int i = 0U; i < VA_REGIONS; i++) {
va_region = (xlat_addr_region_id_t)i;
@@ -1338,7 +1328,7 @@
}
}
-TEST(xlat_tests_G2, xlat_unmap_memory_page_TC2)
+void xlat_unmap_memory_page_tc2(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1535,7 +1525,7 @@
}
}
-ASSERT_TEST(xlat_tests_G2, xlat_unmap_memory_page_TC3)
+void xlat_unmap_memory_page_tc3(void)
{
/***************************************************************
* TEST CASE 3:
@@ -1549,7 +1539,7 @@
test_helpers_fail_if_no_assert_failed();
}
-TEST(xlat_tests_G2, xlat_map_memory_page_with_attrs_TC1)
+void xlat_map_memory_page_with_attrs_tc1(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -1587,8 +1577,8 @@
mmap_count = 3;
base_lvl = XLAT_TEST_MIN_LVL();
- /* The first look-up level that supports blocks is L1 */
- for (end_lvl = 1; end_lvl <= XLAT_TABLE_LEVEL_MAX; end_lvl++) {
+ end_lvl = XLAT_MIN_BLOCK_LVL();
+ for (; end_lvl <= XLAT_TABLE_LEVEL_MAX; end_lvl++) {
for (int i = 0U; i < VA_REGIONS; i++) {
va_region = (xlat_addr_region_id_t)i;
@@ -1744,7 +1734,7 @@
}
}
-TEST(xlat_tests_G2, xlat_map_memory_page_with_attrs_TC2)
+void xlat_map_memory_page_with_attrs_tc2(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -2036,7 +2026,7 @@
}
}
-ASSERT_TEST(xlat_tests_G2, xlat_map_memory_page_with_attrs_TC3)
+void xlat_map_memory_page_with_attrs_tc3(void)
{
/***************************************************************
* TEST CASE 3:
@@ -2144,7 +2134,7 @@
tcr, exp_tcr);
}
-TEST(xlat_tests_G2, xlat_arch_setup_mmu_cfg_TC1)
+void xlat_arch_setup_mmu_cfg_tc1(void)
{
struct xlat_ctx ctx[2U];
struct xlat_ctx_cfg cfg[2U];
@@ -2220,7 +2210,7 @@
validate_tcr_el2(&ctx[0U], &ctx[1U]);
}
-TEST(xlat_tests_G2, xlat_arch_setup_mmu_cfg_TC2)
+void xlat_arch_setup_mmu_cfg_tc2(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -2323,7 +2313,7 @@
}
-ASSERT_TEST(xlat_tests_G2, xlat_arch_setup_mmu_cfg_TC3)
+void xlat_arch_setup_mmu_cfg_tc3(void)
{
/***************************************************************
* TEST CASE 3:
@@ -2336,7 +2326,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_arch_setup_mmu_cfg_TC4)
+void xlat_arch_setup_mmu_cfg_tc4(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -2363,7 +2353,7 @@
test_helpers_fail_if_no_assert_failed();
}
-ASSERT_TEST(xlat_tests_G2, xlat_arch_setup_mmu_cfg_TC5)
+void xlat_arch_setup_mmu_cfg_tc5(void)
{
struct xlat_ctx ctx;
struct xlat_ctx_cfg cfg;
@@ -2390,7 +2380,7 @@
test_helpers_fail_if_no_assert_failed();
}
-TEST(xlat_tests_G2, xlat_get_oa_from_tte_TC1)
+void xlat_get_oa_from_tte_tc1(void)
{
uint64_t test_tte, val_addr, output_addr;
@@ -2440,42 +2430,3 @@
"Test xlat_get_oa_from_tte, LPA2 not supported: OA = %p - Expected = %p",
(void *)output_addr, (void *)val_addr);
}
-
-IGNORE_TEST(xlat_tests_G2, xlat_write_tte_TC1)
-{
- /*
- * xlat_write_tte() is implemented as an assembler function
- * for target AArch64 Architecture. There is a C stub for the
- * fake_host platform which we do not need to test.
- *
- * This test can therefore be ignored.
- */
-
- TEST_EXIT;
-}
-
-IGNORE_TEST(xlat_tests_G2, xlat_read_tte_TC1)
-{
- /*
- * xlat_read_tte() is implemented as an assembler function
- * for target AArch64 Architecture. There is a C stub for the
- * fake_host platform which we do not need to test.
- *
- * This test can therefore be ignored.
- */
-
- TEST_EXIT;
-}
-
-IGNORE_TEST(xlat_tests_G2, xlat_enable_mmu_el2_TC1)
-{
- /*
- * xlat_enable_mmu_el2() is implemented as an assembler function
- * for target AArch64 Architecture. There is a C stub for the
- * fake_host platform which we do not need to test.
- *
- * This test can therefore be ignored.
- */
-
- TEST_EXIT;
-}
diff --git a/lib/xlat/tests/xlat_tests_lpa2.cpp b/lib/xlat/tests/xlat_tests_lpa2.cpp
new file mode 100644
index 0000000..aa8ab2e
--- /dev/null
+++ b/lib/xlat/tests/xlat_tests_lpa2.cpp
@@ -0,0 +1,297 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: Copyright TF-RMM Contributors.
+ */
+
+#include <CppUTest/CommandLineTestRunner.h>
+#include <CppUTest/TestHarness.h>
+#include <xlat_tests_base.h>
+
+extern "C" {
+#include <test_helpers.h>
+#include <xlat_test_helpers.h>
+}
+
+TEST_GROUP(xlat_tests_LPA2) {
+ TEST_SETUP()
+ {
+ xlat_test_setup(LPA2_ENABLED);
+ }
+
+ TEST_TEARDOWN()
+ {}
+};
+
+TEST(xlat_tests_LPA2, map_region_full_spec_TC1)
+{
+ map_region_full_spec_tc1();
+}
+
+TEST(xlat_tests_LPA2, map_region_TC1)
+{
+ map_region_tc1();
+}
+
+TEST(xlat_tests_LPA2, map_region_flat_TC1)
+{
+ map_region_flat_tc1();
+}
+
+TEST(xlat_tests_LPA2, map_region_transient_TC1)
+{
+ map_region_transient_tc1();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC1)
+{
+ xlat_ctx_cfg_init_tc1();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC2)
+{
+ xlat_ctx_cfg_init_tc2();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC3)
+{
+ xlat_ctx_cfg_init_tc3();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC4)
+{
+ xlat_ctx_cfg_init_tc4();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC5)
+{
+ xlat_ctx_cfg_init_tc5();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC6)
+{
+ xlat_ctx_cfg_init_tc6();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC7)
+{
+ xlat_ctx_cfg_init_tc7();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC8)
+{
+ xlat_ctx_cfg_init_tc8();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC9)
+{
+ xlat_ctx_cfg_init_tc9();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC10)
+{
+ xlat_ctx_cfg_init_tc10();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC11)
+{
+ xlat_ctx_cfg_init_tc11();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_cfg_init_TC12)
+{
+ xlat_ctx_cfg_init_tc12();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_init_TC1)
+{
+ xlat_ctx_init_tc1();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_init_TC2)
+{
+ xlat_ctx_init_tc2();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_init_TC3)
+{
+ xlat_ctx_init_tc3();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_ctx_init_TC4)
+{
+ xlat_ctx_init_tc4();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_init_TC5)
+{
+ xlat_ctx_init_tc5();
+}
+
+TEST(xlat_tests_LPA2, xlat_ctx_init_TC6)
+{
+ xlat_ctx_init_tc6();
+}
+
+TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC1)
+{
+ xlat_get_llt_from_va_tc1();
+}
+
+TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC2)
+{
+ xlat_get_llt_from_va_tc2();
+}
+
+TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC3)
+{
+ xlat_get_llt_from_va_tc3();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC4)
+{
+ xlat_get_llt_from_va_tc4();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC5)
+{
+ xlat_get_llt_from_va_tc5();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC6)
+{
+ xlat_get_llt_from_va_tc6();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC7)
+{
+ xlat_get_llt_from_va_tc7();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC8)
+{
+ xlat_get_llt_from_va_tc8();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_llt_from_va_TC9)
+{
+ xlat_get_llt_from_va_tc9();
+}
+
+TEST(xlat_tests_LPA2, xlat_get_tte_ptr_TC1)
+{
+ xlat_get_tte_ptr_tc1();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_tte_ptr_TC2)
+{
+ xlat_get_tte_ptr_tc2();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_tte_ptr_TC3)
+{
+ xlat_get_tte_ptr_tc3();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_get_tte_ptr_TC4)
+{
+ xlat_get_tte_ptr_tc4();
+}
+
+TEST(xlat_tests_LPA2, xlat_unmap_memory_page_TC1)
+{
+ xlat_unmap_memory_page_tc1();
+}
+
+TEST(xlat_tests_LPA2, xlat_unmap_memory_page_TC2)
+{
+ xlat_unmap_memory_page_tc2();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_unmap_memory_page_TC3)
+{
+ xlat_unmap_memory_page_tc3();
+}
+
+TEST(xlat_tests_LPA2, xlat_map_memory_page_with_attrs_TC1)
+{
+ xlat_map_memory_page_with_attrs_tc1();
+}
+
+TEST(xlat_tests_LPA2, xlat_map_memory_page_with_attrs_TC2)
+{
+ xlat_map_memory_page_with_attrs_tc2();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_map_memory_page_with_attrs_TC3)
+{
+ xlat_map_memory_page_with_attrs_tc3();
+}
+
+TEST(xlat_tests_LPA2, xlat_arch_setup_mmu_cfg_TC1)
+{
+ xlat_arch_setup_mmu_cfg_tc1();
+}
+
+TEST(xlat_tests_LPA2, xlat_arch_setup_mmu_cfg_TC2)
+{
+ xlat_arch_setup_mmu_cfg_tc2();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_arch_setup_mmu_cfg_TC3)
+{
+ xlat_arch_setup_mmu_cfg_tc3();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_arch_setup_mmu_cfg_TC4)
+{
+ xlat_arch_setup_mmu_cfg_tc4();
+}
+
+ASSERT_TEST(xlat_tests_LPA2, xlat_arch_setup_mmu_cfg_TC5)
+{
+ xlat_arch_setup_mmu_cfg_tc5();
+}
+
+TEST(xlat_tests_LPA2, xlat_get_oa_from_tte_TC1)
+{
+ xlat_get_oa_from_tte_tc1();
+}
+
+IGNORE_TEST(xlat_tests_LPA2, xlat_write_tte_TC1)
+{
+ /*
+ * xlat_write_tte() is implemented as an assembler function
+ * for target AArch64 Architecture. There is a C stub for the
+ * fake_host platform which we do not need to test.
+ *
+ * This test can therefore be ignored.
+ */
+
+ TEST_EXIT;
+}
+
+IGNORE_TEST(xlat_tests_LPA2, xlat_read_tte_TC1)
+{
+ /*
+ * xlat_read_tte() is implemented as an assembler function
+ * for target AArch64 Architecture. There is a C stub for the
+ * fake_host platform which we do not need to test.
+ *
+ * This test can therefore be ignored.
+ */
+
+ TEST_EXIT;
+}
+
+IGNORE_TEST(xlat_tests_LPA2, xlat_enable_mmu_el2_TC1)
+{
+ /*
+ * xlat_enable_mmu_el2() is implemented as an assembler function
+ * for target AArch64 Architecture. There is a C stub for the
+ * fake_host platform which we do not need to test.
+ *
+ * This test can therefore be ignored.
+ */
+
+ TEST_EXIT;
+}
diff --git a/lib/xlat/tests/xlat_tests_no_lpa2.cpp b/lib/xlat/tests/xlat_tests_no_lpa2.cpp
new file mode 100644
index 0000000..844df83
--- /dev/null
+++ b/lib/xlat/tests/xlat_tests_no_lpa2.cpp
@@ -0,0 +1,302 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: Copyright TF-RMM Contributors.
+ */
+
+#include <CppUTest/CommandLineTestRunner.h>
+#include <CppUTest/TestHarness.h>
+#include <xlat_tests_base.h>
+
+extern "C" {
+#include <test_helpers.h>
+#include <xlat_test_helpers.h>
+}
+
+TEST_GROUP(xlat_tests_no_LPA2) {
+ TEST_SETUP()
+ {
+ xlat_test_setup(LPA2_DISABLED);
+ }
+
+ TEST_TEARDOWN()
+ {}
+};
+
+TEST(xlat_tests_no_LPA2, map_region_full_spec_TC1)
+{
+ map_region_full_spec_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, map_region_TC1)
+{
+ map_region_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, map_region_flat_TC1)
+{
+ map_region_flat_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, map_region_transient_TC1)
+{
+ map_region_transient_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC1)
+{
+ xlat_ctx_cfg_init_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC2)
+{
+ xlat_ctx_cfg_init_tc2();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC3)
+{
+ xlat_ctx_cfg_init_tc3();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC4)
+{
+ xlat_ctx_cfg_init_tc4();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC5)
+{
+ xlat_ctx_cfg_init_tc5();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC6)
+{
+ xlat_ctx_cfg_init_tc6();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC7)
+{
+ xlat_ctx_cfg_init_tc7();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC8)
+{
+ xlat_ctx_cfg_init_tc8();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC9)
+{
+ xlat_ctx_cfg_init_tc9();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC10)
+{
+ xlat_ctx_cfg_init_tc10();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC11)
+{
+ xlat_ctx_cfg_init_tc11();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC12)
+{
+ xlat_ctx_cfg_init_tc12();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_cfg_init_TC13)
+{
+ xlat_ctx_cfg_init_tc13();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_init_TC1)
+{
+ xlat_ctx_init_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_init_TC2)
+{
+ xlat_ctx_init_tc2();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_init_TC3)
+{
+ xlat_ctx_init_tc3();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_ctx_init_TC4)
+{
+ xlat_ctx_init_tc4();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_init_TC5)
+{
+ xlat_ctx_init_tc5();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_ctx_init_TC6)
+{
+ xlat_ctx_init_tc6();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC1)
+{
+ xlat_get_llt_from_va_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC2)
+{
+ xlat_get_llt_from_va_tc2();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC3)
+{
+ xlat_get_llt_from_va_tc3();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC4)
+{
+ xlat_get_llt_from_va_tc4();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC5)
+{
+ xlat_get_llt_from_va_tc5();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC6)
+{
+ xlat_get_llt_from_va_tc6();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC7)
+{
+ xlat_get_llt_from_va_tc7();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC8)
+{
+ xlat_get_llt_from_va_tc8();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_llt_from_va_TC9)
+{
+ xlat_get_llt_from_va_tc9();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_get_tte_ptr_TC1)
+{
+ xlat_get_tte_ptr_tc1();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_tte_ptr_TC2)
+{
+ xlat_get_tte_ptr_tc2();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_tte_ptr_TC3)
+{
+ xlat_get_tte_ptr_tc3();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_get_tte_ptr_TC4)
+{
+ xlat_get_tte_ptr_tc4();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_unmap_memory_page_TC1)
+{
+ xlat_unmap_memory_page_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_unmap_memory_page_TC2)
+{
+ xlat_unmap_memory_page_tc2();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_unmap_memory_page_TC3)
+{
+ xlat_unmap_memory_page_tc3();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_map_memory_page_with_attrs_TC1)
+{
+ xlat_map_memory_page_with_attrs_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_map_memory_page_with_attrs_TC2)
+{
+ xlat_map_memory_page_with_attrs_tc2();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_map_memory_page_with_attrs_TC3)
+{
+ xlat_map_memory_page_with_attrs_tc3();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_arch_setup_mmu_cfg_TC1)
+{
+ xlat_arch_setup_mmu_cfg_tc1();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_arch_setup_mmu_cfg_TC2)
+{
+ xlat_arch_setup_mmu_cfg_tc2();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_arch_setup_mmu_cfg_TC3)
+{
+ xlat_arch_setup_mmu_cfg_tc3();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_arch_setup_mmu_cfg_TC4)
+{
+ xlat_arch_setup_mmu_cfg_tc4();
+}
+
+ASSERT_TEST(xlat_tests_no_LPA2, xlat_arch_setup_mmu_cfg_TC5)
+{
+ xlat_arch_setup_mmu_cfg_tc5();
+}
+
+TEST(xlat_tests_no_LPA2, xlat_get_oa_from_tte_TC1)
+{
+ xlat_get_oa_from_tte_tc1();
+}
+
+IGNORE_TEST(xlat_tests_no_LPA2, xlat_write_tte_TC1)
+{
+ /*
+ * xlat_write_tte() is implemented as an assembler function
+ * for target AArch64 Architecture. There is a C stub for the
+ * fake_host platform which we do not need to test.
+ *
+ * This test can therefore be ignored.
+ */
+
+ TEST_EXIT;
+}
+
+IGNORE_TEST(xlat_tests_no_LPA2, xlat_read_tte_TC1)
+{
+ /*
+ * xlat_read_tte() is implemented as an assembler function
+ * for target AArch64 Architecture. There is a C stub for the
+ * fake_host platform which we do not need to test.
+ *
+ * This test can therefore be ignored.
+ */
+
+ TEST_EXIT;
+}
+
+IGNORE_TEST(xlat_tests_no_LPA2, xlat_enable_mmu_el2_TC1)
+{
+ /*
+ * xlat_enable_mmu_el2() is implemented as an assembler function
+ * for target AArch64 Architecture. There is a C stub for the
+ * fake_host platform which we do not need to test.
+ *
+ * This test can therefore be ignored.
+ */
+
+ TEST_EXIT;
+}