feat(rmm): enable alignment fault check
This patch enables Alignment fault check
in SCTLR_EL2 register for RMM built
with RMM_FPU_USE_AT_REL2=OFF option.
Setting SCTLR_EL2.A bit for
RMM_FPU_USE_AT_REL2=ON causes Alignment
fault exception in MbedTls, see
https://github.com/Mbed-TLS/mbedtls/issues/8447
To prevent unaligned access to the fields
of 'memory_header_s' structure
memory buffer allocator macro
MBEDTLS_MEMORY_ALIGN_MULTIPLE is set to 8
and 16 byte alignment is added for
'fpu_regs' and 'sve_regs' structures.
Alignment of 'unsigned char measurement[][]'
of 'rd' structure is set to 8 to pass
alignment check for
measurement_value_part = (unsigned long *)
&(rd->measurement[idx][i * sizeof(unsigned long)]);
in handle_rsi_measurement_read().
Change-Id: I6751b4125a6055999417c639651f6aac12eed3ef
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
diff --git a/lib/arch/include/arch.h b/lib/arch/include/arch.h
index 694d85d..55da52c 100644
--- a/lib/arch/include/arch.h
+++ b/lib/arch/include/arch.h
@@ -694,6 +694,7 @@
(UL(1) << 11) /* TODO: ARMv8.5-CSEH, otherwise RES1 */)
#define SCTLR_ELx_M_BIT (UL(1) << 0)
+#define SCTLR_ELx_A_BIT (UL(1) << 1)
#define SCTLR_ELx_C_BIT (UL(1) << 2)
#define SCTLR_ELx_SA_BIT (UL(1) << 3)
#define SCTLR_ELx_SA0_BIT (UL(1) << 4)
@@ -722,7 +723,7 @@
SCTLR_ELx_nTWI_BIT | SCTLR_ELx_EOS_BIT | SCTLR_ELx_nAA_BIT | \
SCTLR_ELx_CP15BEN_BIT | SCTLR_ELx_SA0_BIT | SCTLR_ELx_SA_BIT)
-#define SCTLR_EL2_INIT (SCTLR_ELx_C_BIT /* Data accesses are cacheable
+#define SCTLR_EL2_BITS (SCTLR_ELx_C_BIT /* Data accesses are cacheable
* as per translation tables */ | \
/* SCTLR_EL2_M = 0 (MMU disabled) */ \
/* SCTLR_EL2_A = 0
@@ -757,6 +758,13 @@
SCTLR_ELx_nTLSMD_BIT /* A32/T32 only */ | \
SCTLR_ELx_LSMAOE_BIT /* A32/T32 only */)
+#ifdef RMM_FPU_USE_AT_REL2
+#define SCTLR_EL2_INIT SCTLR_EL2_BITS
+#else
+#define SCTLR_EL2_INIT (SCTLR_EL2_BITS | \
+ SCTLR_ELx_A_BIT /* Alignment fault check enable */)
+#endif
+
#define SCTLR_EL2_RUNTIME (SCTLR_EL2_INIT | \
SCTLR_ELx_M_BIT /* MMU enabled */)