commit 93f5ec5b98abf3d9a2f06268fd0e9fd65721a76e
author AlexeiFedorov <Alexei.Fedorov@arm.com> Thu Aug 31 14:26:53 2023 +0100
committer Soby Mathew <soby.mathew@arm.com> Fri Sep 08 12:23:58 2023 +0100
tree 21a8767d48ab45b6ef8988ec488441041e108354
parent 99a87a27ccec9ec3438a8727848463b042ec22b3

fix(rmm): fix MISRA C:2012 Rule 10.4

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I03630ef02c8c294a552ad10523d9c78091ce161a

lib/realm/src/s2tt.c

diff --git a/lib/realm/src/s2tt.c b/lib/realm/src/s2tt.c
index 9269a85..646bd65 100644
--- a/lib/realm/src/s2tt.c
+++ b/lib/realm/src/s2tt.c
@@ -26,7 +26,7 @@
  * The maximum number of bits supported by the RMM for a stage 2 translation
  * output address (including stage 2 table entries).
  */
-#define S2TTE_OA_BITS			48
+#define S2TTE_OA_BITS			48U
 
 #define DESC_TYPE_MASK			3UL
 #define S2TTE_Lx_INVALID		0UL
@@ -107,19 +107,19 @@
  */
 
 #define S2TTE_INVALID_HIPAS_SHIFT	2
-#define S2TTE_INVALID_HIPAS_WIDTH	3
+#define S2TTE_INVALID_HIPAS_WIDTH	3U
 #define S2TTE_INVALID_HIPAS_MASK	MASK(S2TTE_INVALID_HIPAS)
 
-#define S2TTE_INVALID_HIPAS_UNASSIGNED	(INPLACE(S2TTE_INVALID_HIPAS, 0))
-#define S2TTE_INVALID_HIPAS_ASSIGNED	(INPLACE(S2TTE_INVALID_HIPAS, 1))
+#define S2TTE_INVALID_HIPAS_UNASSIGNED	(INPLACE(S2TTE_INVALID_HIPAS, 0UL))
+#define S2TTE_INVALID_HIPAS_ASSIGNED	(INPLACE(S2TTE_INVALID_HIPAS, 1UL))
 
 #define S2TTE_INVALID_RIPAS_SHIFT	5
-#define S2TTE_INVALID_RIPAS_WIDTH	2
+#define S2TTE_INVALID_RIPAS_WIDTH	2U
 #define S2TTE_INVALID_RIPAS_MASK	MASK(S2TTE_INVALID_RIPAS)
 
-#define S2TTE_INVALID_RIPAS_EMPTY	(INPLACE(S2TTE_INVALID_RIPAS, 0))
-#define S2TTE_INVALID_RIPAS_RAM		(INPLACE(S2TTE_INVALID_RIPAS, 1))
-#define S2TTE_INVALID_RIPAS_DESTROYED	(INPLACE(S2TTE_INVALID_RIPAS, 2))
+#define S2TTE_INVALID_RIPAS_EMPTY	(INPLACE(S2TTE_INVALID_RIPAS, 0UL))
+#define S2TTE_INVALID_RIPAS_RAM		(INPLACE(S2TTE_INVALID_RIPAS, 1UL))
+#define S2TTE_INVALID_RIPAS_DESTROYED	(INPLACE(S2TTE_INVALID_RIPAS, 2UL))
 
 #define S2TTE_INVALID_UNPROTECTED	0x0UL