fix(rmm): fix MISRA C:2012 Rule 10.4
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I03630ef02c8c294a552ad10523d9c78091ce161a
diff --git a/lib/arch/include/arch.h b/lib/arch/include/arch.h
index 1e0e6a1..6146bec 100644
--- a/lib/arch/include/arch.h
+++ b/lib/arch/include/arch.h
@@ -161,8 +161,8 @@
#define HCR_VSE (UL(1) << 8)
#define HCR_BSU_SHIFT 10
-#define HCR_BSU_WIDTH 2
-#define HCR_BSU_IS INPLACE(HCR_BSU, 1) /* Barriers are promoted to IS */
+#define HCR_BSU_WIDTH U(2)
+#define HCR_BSU_IS INPLACE(HCR_BSU, UL(1)) /* Barriers are promoted to IS */
#define HCR_FB (UL(1) << 9)
#define HCR_VI (UL(1) << 7)
@@ -180,7 +180,7 @@
#define HCR_EL2_INIT (HCR_TGE | HCR_E2H | HCR_TEA)
#define MAIR_ELx_ATTR0_SHIFT 0
-#define MAIR_ELx_ATTR0_WIDTH 8
+#define MAIR_ELx_ATTR0_WIDTH U(8)
/*******************************************************************************
* Definitions of MAIR encodings for device and normal memory
@@ -244,67 +244,67 @@
#define TTBR_CNP_BIT UL(1)
#define TTBRx_EL2_CnP_SHIFT 0
-#define TTBRx_EL2_CnP_WIDTH 1
+#define TTBRx_EL2_CnP_WIDTH U(1)
#define TTBRx_EL2_BADDR_SHIFT 1
-#define TTBRx_EL2_BADDR_WIDTH 47
+#define TTBRx_EL2_BADDR_WIDTH U(47)
#define TTBRx_EL2_ASID_SHIFT 48
-#define TTBRx_EL2_ASID_WIDTH 16
+#define TTBRx_EL2_ASID_WIDTH U(16)
/*
* VTTBR Definitions
*/
#define VTTBR_EL2_VMID_SHIFT 48
-#define VTTBR_EL2_VMID_WIDTH 16
+#define VTTBR_EL2_VMID_WIDTH U(16)
/*
* ESR Definitions
*/
#define ESR_EL2_EC_SHIFT 26
-#define ESR_EL2_EC_WIDTH 6
+#define ESR_EL2_EC_WIDTH U(6)
#define ESR_EL2_IL_SHIFT 25
-#define ESR_EL2_IL_WIDTH 1
+#define ESR_EL2_IL_WIDTH U(1)
#define ESR_EL2_ISS_SHIFT 0
-#define ESR_EL2_ISS_WIDTH 25
+#define ESR_EL2_ISS_WIDTH U(25)
-#define ESR_EL2_EC_UNKNOWN INPLACE(ESR_EL2_EC, 0)
-#define ESR_EL2_EC_WFX INPLACE(ESR_EL2_EC, 1)
-#define ESR_EL2_EC_FPU INPLACE(ESR_EL2_EC, 7)
-#define ESR_EL2_EC_SVC INPLACE(ESR_EL2_EC, 21)
-#define ESR_EL2_EC_HVC INPLACE(ESR_EL2_EC, 22)
-#define ESR_EL2_EC_SMC INPLACE(ESR_EL2_EC, 23)
-#define ESR_EL2_EC_SYSREG INPLACE(ESR_EL2_EC, 24)
-#define ESR_EL2_EC_SVE INPLACE(ESR_EL2_EC, 25)
-#define ESR_EL2_EC_INST_ABORT INPLACE(ESR_EL2_EC, 32)
-#define ESR_EL2_EC_INST_ABORT_SEL INPLACE(ESR_EL2_EC, 33)
-#define ESR_EL2_EC_DATA_ABORT INPLACE(ESR_EL2_EC, 36)
-#define ESR_EL2_EC_DATA_ABORT_SEL INPLACE(ESR_EL2_EC, 37)
-#define ESR_EL2_EC_SERROR INPLACE(ESR_EL2_EC, 47)
+#define ESR_EL2_EC_UNKNOWN INPLACE(ESR_EL2_EC, UL(0))
+#define ESR_EL2_EC_WFX INPLACE(ESR_EL2_EC, UL(1))
+#define ESR_EL2_EC_FPU INPLACE(ESR_EL2_EC, UL(7))
+#define ESR_EL2_EC_SVC INPLACE(ESR_EL2_EC, UL(21))
+#define ESR_EL2_EC_HVC INPLACE(ESR_EL2_EC, UL(22))
+#define ESR_EL2_EC_SMC INPLACE(ESR_EL2_EC, UL(23))
+#define ESR_EL2_EC_SYSREG INPLACE(ESR_EL2_EC, UL(24))
+#define ESR_EL2_EC_SVE INPLACE(ESR_EL2_EC, UL(25))
+#define ESR_EL2_EC_INST_ABORT INPLACE(ESR_EL2_EC, UL(32))
+#define ESR_EL2_EC_INST_ABORT_SEL INPLACE(ESR_EL2_EC, UL(33))
+#define ESR_EL2_EC_DATA_ABORT INPLACE(ESR_EL2_EC, UL(36))
+#define ESR_EL2_EC_DATA_ABORT_SEL INPLACE(ESR_EL2_EC, UL(37))
+#define ESR_EL2_EC_SERROR INPLACE(ESR_EL2_EC, UL(47))
/* Data/Instruction Abort ESR fields */
#define ESR_EL2_ABORT_ISV_BIT (UL(1) << 24)
#define ESR_EL2_ABORT_SAS_SHIFT 22
-#define ESR_EL2_ABORT_SAS_WIDTH 2
+#define ESR_EL2_ABORT_SAS_WIDTH U(2)
-#define ESR_EL2_ABORT_SAS_BYTE_VAL 0
-#define ESR_EL2_ABORT_SAS_HWORD_VAL 1
-#define ESR_EL2_ABORT_SAS_WORD_VAL 2
-#define ESR_EL2_ABORT_SAS_DWORD_VAL 3
+#define ESR_EL2_ABORT_SAS_BYTE_VAL 0U
+#define ESR_EL2_ABORT_SAS_HWORD_VAL 1U
+#define ESR_EL2_ABORT_SAS_WORD_VAL 2U
+#define ESR_EL2_ABORT_SAS_DWORD_VAL 3U
#define ESR_EL2_ABORT_SSE_BIT (UL(1) << 21)
#define ESR_EL2_ABORT_SRT_SHIFT 16
-#define ESR_EL2_ABORT_SRT_WIDTH 5
+#define ESR_EL2_ABORT_SRT_WIDTH U(5)
#define ESR_EL2_ABORT_SET_SHIFT 11
-#define ESR_EL2_ABORT_SET_WIDTH 2
-#define ESR_EL2_ABORT_SET_UER INPLACE(ESR_EL2_ABORT_SET, 0)
-#define ESR_EL2_ABORT_SET_UC INPLACE(ESR_EL2_ABORT_SET, 2)
-#define ESR_EL2_ABORT_SET_UEO INPLACE(ESR_EL2_ABORT_SET, 3)
+#define ESR_EL2_ABORT_SET_WIDTH U(2)
+#define ESR_EL2_ABORT_SET_UER INPLACE(ESR_EL2_ABORT_SET, UL(0))
+#define ESR_EL2_ABORT_SET_UC INPLACE(ESR_EL2_ABORT_SET, UL(2))
+#define ESR_EL2_ABORT_SET_UEO INPLACE(ESR_EL2_ABORT_SET, UL(3))
#define ESR_EL2_ABORT_SF_BIT (UL(1) << 15)
#define ESR_EL2_ABORT_FNV_BIT (UL(1) << 10)
@@ -312,17 +312,17 @@
#define ESR_EL2_ABORT_S1PTW_BIT (UL(1) << 7)
#define ESR_EL2_ABORT_WNR_BIT (UL(1) << 6)
#define ESR_EL2_ABORT_FSC_SHIFT 0
-#define ESR_EL2_ABORT_FSC_WIDTH 6
+#define ESR_EL2_ABORT_FSC_WIDTH U(6)
-#define ESR_EL2_ABORT_FSC_TRANSLATION_FAULT 0x04
-#define ESR_EL2_ABORT_FSC_PERMISSION_FAULT 0x0c
-#define ESR_EL2_ABORT_FSC_TRANSLATION_FAULT_L0 0x04
-#define ESR_EL2_ABORT_FSC_SEA 0x10
-#define ESR_EL2_ABORT_FSC_SEA_TTW_START 0x13
-#define ESR_EL2_ABORT_FSC_SEA_TTW_END 0x17
-#define ESR_EL2_ABORT_FSC_GPF 0x28
+#define ESR_EL2_ABORT_FSC_TRANSLATION_FAULT UL(0x04)
+#define ESR_EL2_ABORT_FSC_PERMISSION_FAULT UL(0x0c)
+#define ESR_EL2_ABORT_FSC_TRANSLATION_FAULT_L0 UL(0x04)
+#define ESR_EL2_ABORT_FSC_SEA UL(0x10)
+#define ESR_EL2_ABORT_FSC_SEA_TTW_START UL(0x13)
+#define ESR_EL2_ABORT_FSC_SEA_TTW_END UL(0x17)
+#define ESR_EL2_ABORT_FSC_GPF UL(0x28)
#define ESR_EL2_ABORT_FSC_LEVEL_SHIFT 0
-#define ESR_EL2_ABORT_FSC_LEVEL_WIDTH 2
+#define ESR_EL2_ABORT_FSC_LEVEL_WIDTH U(2)
/* The ESR fields that are reported to the host on Instr./Data Synchronous Abort */
#define ESR_NONEMULATED_ABORT_MASK ( \
@@ -340,19 +340,19 @@
ESR_EL2_ABORT_WNR_BIT)
#define ESR_EL2_SERROR_DFSC_SHIFT 0
-#define ESR_EL2_SERROR_DFSC_WIDTH 6
-#define ESR_EL2_SERROR_DFSC_UNCAT INPLACE(ESR_EL2_SERROR_DFSC, 0)
-#define ESR_EL2_SERROR_DFSC_ASYNC INPLACE(ESR_EL2_SERROR_DFSC, 1)
+#define ESR_EL2_SERROR_DFSC_WIDTH U(6)
+#define ESR_EL2_SERROR_DFSC_UNCAT INPLACE(ESR_EL2_SERROR_DFSC, UL(0))
+#define ESR_EL2_SERROR_DFSC_ASYNC INPLACE(ESR_EL2_SERROR_DFSC, UL(1))
#define ESR_EL2_SERROR_EA_BIT (UL(1) << 9)
#define ESR_EL2_SERROR_AET_SHIFT 10
-#define ESR_EL2_SERROR_AET_WIDTH 3
-#define ESR_EL2_SERROR_AET_UC INPLACE(ESR_EL2_SERROR_AET, 0)
-#define ESR_EL2_SERROR_AET_UEU INPLACE(ESR_EL2_SERROR_AET, 1)
-#define ESR_EL2_SERROR_AET_UEO INPLACE(ESR_EL2_SERROR_AET, 2)
-#define ESR_EL2_SERROR_AET_UER INPLACE(ESR_EL2_SERROR_AET, 3)
-#define ESR_EL2_SERROR_AET_CE INPLACE(ESR_EL2_SERROR_AET, 6)
+#define ESR_EL2_SERROR_AET_WIDTH U(3)
+#define ESR_EL2_SERROR_AET_UC INPLACE(ESR_EL2_SERROR_AET, UL(0))
+#define ESR_EL2_SERROR_AET_UEU INPLACE(ESR_EL2_SERROR_AET, UL(1))
+#define ESR_EL2_SERROR_AET_UEO INPLACE(ESR_EL2_SERROR_AET, UL(2))
+#define ESR_EL2_SERROR_AET_UER INPLACE(ESR_EL2_SERROR_AET, UL(3))
+#define ESR_EL2_SERROR_AET_CE INPLACE(ESR_EL2_SERROR_AET, UL(6))
#define ESR_EL2_SERROR_IESB_BIT (UL(1) << 13)
#define ESR_EL2_SERROR_IDS_BIT (UL(1) << 24)
@@ -365,29 +365,29 @@
MASK(ESR_EL2_SERROR_DFSC))
#define ESR_EL2_SYSREG_TRAP_OP0_SHIFT 20
-#define ESR_EL2_SYSREG_TRAP_OP0_WIDTH 2
+#define ESR_EL2_SYSREG_TRAP_OP0_WIDTH U(2)
#define ESR_EL2_SYSREG_TRAP_OP2_SHIFT 17
-#define ESR_EL2_SYSREG_TRAP_OP2_WIDTH 3
+#define ESR_EL2_SYSREG_TRAP_OP2_WIDTH U(3)
#define ESR_EL2_SYSREG_TRAP_OP1_SHIFT 14
-#define ESR_EL2_SYSREG_TRAP_OP1_WIDTH 3
+#define ESR_EL2_SYSREG_TRAP_OP1_WIDTH U(3)
#define ESR_EL2_SYSREG_TRAP_CRN_SHIFT 10
-#define ESR_EL2_SYSREG_TRAP_CRN_WIDTH 4
+#define ESR_EL2_SYSREG_TRAP_CRN_WIDTH U(4)
#define ESR_EL2_SYSREG_TRAP_RT_SHIFT 5
-#define ESR_EL2_SYSREG_TRAP_RT_WIDTH 5
+#define ESR_EL2_SYSREG_TRAP_RT_WIDTH U(5)
#define ESR_EL2_SYSREG_TRAP_CRM_SHIFT 1
-#define ESR_EL2_SYSREG_TRAP_CRM_WIDTH 4
+#define ESR_EL2_SYSREG_TRAP_CRM_WIDTH U(4)
/* WFx ESR fields */
#define ESR_EL2_WFx_TI_BIT (UL(1) << 0)
/* xVC ESR fields */
#define ESR_EL2_xVC_IMM_SHIFT 0
-#define ESR_EL2_xVC_IMM_WIDTH 16
+#define ESR_EL2_xVC_IMM_WIDTH U(16)
/* ID_AA64DFR0_EL1 definitions */
#define ID_AA64DFR0_EL1_HPMN0_SHIFT UL(60)
@@ -462,7 +462,7 @@
#define ID_AA64PFR0_EL1_SVE_WIDTH UL(4)
#define ID_AA64PFR0_EL1_AMU_SHIFT UL(44)
-#define ID_AA64PFR0_EL1_AMU_WIDTH 4
+#define ID_AA64PFR0_EL1_AMU_WIDTH UL(4)
/* ID_AA64PFR1_EL1 definitions */
#define ID_AA64PFR1_EL1_MTE_SHIFT UL(8)
@@ -538,27 +538,27 @@
/* HPFAR_EL2 definitions */
#define HPFAR_EL2_FIPA_SHIFT 4
-#define HPFAR_EL2_FIPA_WIDTH 40
+#define HPFAR_EL2_FIPA_WIDTH U(40)
#define HPFAR_EL2_FIPA_OFFSET 8
/* SPSR definitions */
#define SPSR_EL2_MODE_SHIFT 0
-#define SPSR_EL2_MODE_WIDTH 4
-#define SPSR_EL2_MODE_EL0t INPLACE(SPSR_EL2_MODE, 0)
+#define SPSR_EL2_MODE_WIDTH U(4)
+#define SPSR_EL2_MODE_EL0t INPLACE(SPSR_EL2_MODE, UL(0))
#define SPSR_EL2_MODE_SHIFT 0
-#define SPSR_EL2_MODE_WIDTH 4
-#define SPSR_EL2_MODE_EL1h INPLACE(SPSR_EL2_MODE, 5)
-#define SPSR_EL2_MODE_EL1t INPLACE(SPSR_EL2_MODE, 4)
+#define SPSR_EL2_MODE_WIDTH U(4)
+#define SPSR_EL2_MODE_EL1h INPLACE(SPSR_EL2_MODE, UL(5))
+#define SPSR_EL2_MODE_EL1t INPLACE(SPSR_EL2_MODE, UL(4))
/* FIXME: DAIF definitions are redundant here. Might need unification. */
#define SPSR_EL2_nRW_SHIFT 4
-#define SPSR_EL2_nRW_WIDTH 1
-#define SPSR_EL2_nRW_AARCH64 INPLACE(SPSR_EL2_nRW, 0)
-#define SPSR_EL2_nRW_AARCH32 INPLACE(SPSR_EL2_nRW, 1)
+#define SPSR_EL2_nRW_WIDTH U(1)
+#define SPSR_EL2_nRW_AARCH64 INPLACE(SPSR_EL2_nRW, UL(0))
+#define SPSR_EL2_nRW_AARCH32 INPLACE(SPSR_EL2_nRW, UL(1))
#define SPSR_EL2_DAIF_SHIFT 6
-#define SPSR_EL2_AIF_SHIFT 6
+#define SPSR_EL2_AIF_SHIFT U(6)
#define DAIF_FIQ_BIT (UL(1) << 0)
#define DAIF_IRQ_BIT (UL(1) << 1)
@@ -591,35 +591,35 @@
/* VTCR definitions */
#define VTCR_T0SZ_SHIFT 0
-#define VTCR_T0SZ_WIDTH 6
+#define VTCR_T0SZ_WIDTH U(6)
#define VTCR_SL0_SHIFT 6
-#define VTCR_SL0_WIDTH 2
+#define VTCR_SL0_WIDTH U(2)
-#define VTCR_SL0_4K_L2 INPLACE(VTCR_SL0, 0)
-#define VTCR_SL0_4K_L1 INPLACE(VTCR_SL0, 1)
-#define VTCR_SL0_4K_L0 INPLACE(VTCR_SL0, 2)
-#define VTCR_SL0_4K_L3 INPLACE(VTCR_SL0, 3)
+#define VTCR_SL0_4K_L2 INPLACE(VTCR_SL0, UL(0))
+#define VTCR_SL0_4K_L1 INPLACE(VTCR_SL0, UL(1))
+#define VTCR_SL0_4K_L0 INPLACE(VTCR_SL0, UL(2))
+#define VTCR_SL0_4K_L3 INPLACE(VTCR_SL0, UL(3))
#define VTCR_IRGN0_SHIFT 8
-#define VTCR_IRGN0_WIDTH 2
-#define VTCR_IRGN0_WBRAWA INPLACE(VTCR_IRGN0, 1)
+#define VTCR_IRGN0_WIDTH U(2)
+#define VTCR_IRGN0_WBRAWA INPLACE(VTCR_IRGN0, UL(1))
#define VTCR_ORGN0_SHIFT 10
-#define VTCR_ORGN0_WIDTH 2
-#define VTCR_ORGN0_WBRAWA INPLACE(VTCR_ORGN0, 1)
+#define VTCR_ORGN0_WIDTH U(2)
+#define VTCR_ORGN0_WBRAWA INPLACE(VTCR_ORGN0, UL(1))
#define VTCR_SH0_SHIFT 12
-#define VTCR_SH0_WIDTH 2
-#define VTCR_SH0_IS INPLACE(VTCR_SH0, 3)
+#define VTCR_SH0_WIDTH U(2)
+#define VTCR_SH0_IS INPLACE(VTCR_SH0, UL(3))
#define VTCR_TG0_SHIFT 14
-#define VTCR_TG0_WIDTH 2
-#define VTCR_TG0_4K INPLACE(VTCR_TG0, 0)
+#define VTCR_TG0_WIDTH U(2)
+#define VTCR_TG0_4K INPLACE(VTCR_TG0, UL(0))
#define VTCR_PS_SHIFT 16
-#define VTCR_PS_WIDTH 3
-#define VTCR_PS_40 INPLACE(VTCR_PS, 2)
+#define VTCR_PS_WIDTH U(3)
+#define VTCR_PS_40 INPLACE(VTCR_PS, UL(2))
#define VTCR_VS (UL(1) << 19)
#define VTCR_NSA (UL(1) << 30)
@@ -640,7 +640,7 @@
/* PMCR_EL0 Definitions */
#define PMCR_EL0_N_SHIFT 11
-#define PMCR_EL0_N_WIDTH 5
+#define PMCR_EL0_N_WIDTH U(5)
#define PMCR_EL0_LC_BIT (UL(1) << 6)
#define PMCR_EL0_DP_BIT (UL(1) << 5)
#define PMCR_EL0_C_BIT (UL(1) << 2)
@@ -729,16 +729,19 @@
#define CPTR_EL2_RES1 ((UL(1) << 13) | (UL(1) << 12) | (UL(1) << 9) | 0xff)
#define CPTR_EL2_TTA (UL(1) << 28)
#define CPTR_EL2_TAM (UL(1) << 30)
+
#define CPTR_EL2_FPEN_SHIFT UL(20)
#define CPTR_EL2_FPEN_WIDTH UL(2)
-#define CPTR_EL2_FPEN_TRAP_ALL_00 0x0
-#define CPTR_EL2_FPEN_TRAP_TGE_01 0x1
-#define CPTR_EL2_FPEN_TRAP_ALL_10 0x2
-#define CPTR_EL2_FPEN_NO_TRAP_11 0x3
+#define CPTR_EL2_FPEN_TRAP_ALL_00 UL(0)
+#define CPTR_EL2_FPEN_TRAP_TGE_01 UL(1)
+#define CPTR_EL2_FPEN_TRAP_ALL_10 UL(2)
+#define CPTR_EL2_FPEN_NO_TRAP_11 UL(3)
+
#define CPTR_EL2_ZEN_SHIFT UL(16)
#define CPTR_EL2_ZEN_WIDTH UL(2)
-#define CPTR_EL2_ZEN_TRAP_ALL_00 UL(0x0)
-#define CPTR_EL2_ZEN_NO_TRAP_11 UL(0x3)
+#define CPTR_EL2_ZEN_TRAP_ALL_00 UL(0)
+#define CPTR_EL2_ZEN_NO_TRAP_11 UL(3)
+
/* Trap all FPU/SVE accesses */
#define CPTR_EL2_INIT ((CPTR_EL2_ZEN_TRAP_ALL_00 << \
CPTR_EL2_ZEN_SHIFT) | \
@@ -815,22 +818,22 @@
* and Aff0[7:4] of a REC MPIDR value is RES0.
*/
#define MPIDR_EL2_AFF0_SHIFT 0
-#define MPIDR_EL2_AFF0_WIDTH 4
+#define MPIDR_EL2_AFF0_WIDTH U(4)
#define MPIDR_EL2_AFF0_VAL_SHIFT 0
/* Aff1[15:8] - Affinity level 1 */
#define MPIDR_EL2_AFF1_SHIFT 8
-#define MPIDR_EL2_AFF1_WIDTH 8
+#define MPIDR_EL2_AFF1_WIDTH U(8)
#define MPIDR_EL2_AFF1_VAL_SHIFT 4
/* Aff2[23:16] - Affinity level 2 */
#define MPIDR_EL2_AFF2_SHIFT 16
-#define MPIDR_EL2_AFF2_WIDTH 8
+#define MPIDR_EL2_AFF2_WIDTH U(8)
#define MPIDR_EL2_AFF2_VAL_SHIFT 4
/* Aff3[39:32] - Affinity level 3 */
#define MPIDR_EL2_AFF3_SHIFT 32
-#define MPIDR_EL2_AFF3_WIDTH 8
+#define MPIDR_EL2_AFF3_WIDTH U(8)
#define MPIDR_EL2_AFF3_VAL_SHIFT 12
/*
@@ -930,8 +933,8 @@
#define ESR_EL2_SYSREG_ISS_RT(esr) EXTRACT(ESR_EL2_SYSREG_TRAP_RT, esr)
-#define ICC_HPPIR1_EL1_INTID_SHIFT 0
-#define ICC_HPPIR1_EL1_INTID_WIDTH 24
+#define ICC_HPPIR1_EL1_INTID_SHIFT UL(0)
+#define ICC_HPPIR1_EL1_INTID_WIDTH UL(24)
#define CNTHCTL_EL2_EL0PCTEN (UL(1) << UL(0))
#define CNTHCTL_EL2_EL0VCTEN (UL(1) << UL(1))