feat(lib/arch): add support for NS SME context
This feature adds support for Scalable Matrix Extension (SME) in RMM for
handling the Non Secure SME state. If the CPU supports SME and if Realm
accesses FPU/SVE functionality then NS SME state is saved to allow Realm
to use FPU/SVE register state.
Within SME, only the Streaming SVE register state is managed by RMM, as
it shares the register state with FPU/SVE. As Realms do not support SME,
the ZA register state is never managed.
This patch adds necessary changes to support the configuration where
only SME is implemented in the CPU and SVE is not implemented.
This change also caters to the use case of RMM using FPU at REL2 when
built with RMM_FPU_USE_AT_REL2=ON.
Note: SME is not supported for Realms yet.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I127e9aa2e6203ddfe48551443e76e95df476cc35
diff --git a/lib/arch/include/arch_features.h b/lib/arch/include/arch_features.h
index 75d7aa0..386b2ac 100644
--- a/lib/arch/include/arch_features.h
+++ b/lib/arch/include/arch_features.h
@@ -28,6 +28,18 @@
}
/*
+ * Check if SME is enabled
+ * ID_AA64PFR1_EL1.SME, bits [27:24]:
+ * 0b0000 SME architectural state and programmers' model are not implemented.
+ * 0b0001 SME architectural state and programmers' model are implemented.
+ * 0b0010 SME2 implemented. As 0b0001, plus the SME2 ZT0 register.
+ */
+static inline bool is_feat_sme_present(void)
+{
+ return (EXTRACT(ID_AA64PFR1_EL1_SME, read_id_aa64pfr1_el1()) != 0UL);
+}
+
+/*
* Check if RNDR is available
*/
static inline bool is_feat_rng_present(void)