feat(lib/arch): add support for NS SME context
This feature adds support for Scalable Matrix Extension (SME) in RMM for
handling the Non Secure SME state. If the CPU supports SME and if Realm
accesses FPU/SVE functionality then NS SME state is saved to allow Realm
to use FPU/SVE register state.
Within SME, only the Streaming SVE register state is managed by RMM, as
it shares the register state with FPU/SVE. As Realms do not support SME,
the ZA register state is never managed.
This patch adds necessary changes to support the configuration where
only SME is implemented in the CPU and SVE is not implemented.
This change also caters to the use case of RMM using FPU at REL2 when
built with RMM_FPU_USE_AT_REL2=ON.
Note: SME is not supported for Realms yet.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I127e9aa2e6203ddfe48551443e76e95df476cc35
6 files changed