commit 7bb7a70a8d22f4db7fbda6f9520e588a5e5d67e0
author AlexeiFedorov <Alexei.Fedorov@arm.com> Tue Jan 17 17:04:14 2023 +0000
committer AlexeiFedorov <Alexei.Fedorov@arm.com> Fri Jan 27 11:12:07 2023 +0000
tree 57d2a0a820d2722df8568550a29d1e7d4fb9d7b2
parent 297c51b18c935da05efdb41dcac2d02be3d66f47

feat(rmm): report PMU not supported

This patch reports for PMU not being supported by RMM
and adds relevant definitions for Feature Register 0
in accordance with Beta 0 RMM Specification.
It also masks PMUVer field when ID_AA64DFR0_EL1
register is read by Realm.
ID_AA64DFR0_EL1 register mask and set values are
modified to report minimum Debug features supported
by ARM architecture.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I9974dac476df270f309f6bb30d3485ba0af5986e

lib/smc/include/smc-rmi.h

diff --git a/lib/smc/include/smc-rmi.h b/lib/smc/include/smc-rmi.h
index 5442f68..678036b 100644
--- a/lib/smc/include/smc-rmi.h
+++ b/lib/smc/include/smc-rmi.h
@@ -126,6 +126,10 @@
 #define RMI_TABLE		U(3)
 #define RMI_VALID_NS		U(4)
 
+/* RmiFeature enumerations */
+#define RMI_NOT_SUPPORTED			UL(0)
+#define RMI_SUPPORTED				UL(1)
+
 /* RmiFeatureRegister0 format */
 #define RMM_FEATURE_REGISTER_0_INDEX		UL(0)
 
@@ -143,6 +147,12 @@
 #define RMM_FEATURE_REGISTER_0_HASH_SHA_512_SHIFT      UL(29)
 #define RMM_FEATURE_REGISTER_0_HASH_SHA_512_WIDTH      UL(1)
 
+#define RMM_FEATURE_REGISTER_0_PMU_EN_SHIFT		UL(22)
+#define RMM_FEATURE_REGISTER_0_PMU_EN_WIDTH		UL(1)
+
+#define RMM_FEATURE_REGISTER_0_PMU_NUM_CTRS_SHIFT	UL(23)
+#define RMM_FEATURE_REGISTER_0_PMU_NUM_CTRS_WIDTH	UL(5)
+
 /* The RmmRipas enumeration representing realm IPA state */
 #define RMI_EMPTY   (0)
 #define RMI_RAM     (1)