feat(rmm): report PMU not supported
This patch reports for PMU not being supported by RMM
and adds relevant definitions for Feature Register 0
in accordance with Beta 0 RMM Specification.
It also masks PMUVer field when ID_AA64DFR0_EL1
register is read by Realm.
ID_AA64DFR0_EL1 register mask and set values are
modified to report minimum Debug features supported
by ARM architecture.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I9974dac476df270f309f6bb30d3485ba0af5986e
diff --git a/lib/arch/include/arch.h b/lib/arch/include/arch.h
index 5db3d08..dce9172 100644
--- a/lib/arch/include/arch.h
+++ b/lib/arch/include/arch.h
@@ -415,6 +415,66 @@
#define ESR_EL2_xVC_IMM_WIDTH 16
#define ESR_EL2_xVC_IMM_MASK MASK(ESR_EL2_xVC_IMM)
+/* ID_AA64DFR0_EL1 definitions */
+#define ID_AA64DFR0_EL1_HPMN0_SHIFT UL(60)
+#define ID_AA64DFR0_EL1_HPMN0_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_HPMN0_MASK MASK(ID_AA64DFR0_EL1_HPMN0)
+
+#define ID_AA64DFR0_EL1_BRBE_SHIFT UL(52)
+#define ID_AA64DFR0_EL1_BRBE_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_BRBE_MASK MASK(ID_AA64DFR0_EL1_BRBE)
+
+#define ID_AA64DFR0_EL1_MTPMU_SHIFT UL(48)
+#define ID_AA64DFR0_EL1_MTPMU_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_MTPMU_MASK MASK(ID_AA64DFR0_EL1_MTPMU)
+
+#define ID_AA64DFR0_EL1_TraceBuffer_SHIFT UL(44)
+#define ID_AA64DFR0_EL1_TraceBuffer_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_TraceBuffer_MASK MASK(ID_AA64DFR0_EL1_TraceBuffer)
+
+#define ID_AA64DFR0_EL1_TraceFilt_SHIFT UL(40)
+#define ID_AA64DFR0_EL1_TraceFilt_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_TraceFilt_MASK MASK(ID_AA64DFR0_EL1_TraceFilt)
+
+#define ID_AA64DFR0_EL1_DoubleLock_SHIFT UL(36)
+#define ID_AA64DFR0_EL1_DoubleLock_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_DoubleLock_MASK MASK(ID_AA64DFR0_EL1_DoubleLock)
+
+#define ID_AA64DFR0_EL1_PMSVer_SHIFT UL(32)
+#define ID_AA64DFR0_EL1_PMSVer_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_PMSVer_MASK MASK(ID_AA64DFR0_EL1_PMSVer)
+
+#define ID_AA64DFR0_EL1_CTX_CMPS_SHIFT UL(28)
+#define ID_AA64DFR0_EL1_CTX_CMPS_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_CTX_CMPS_MASK MASK(ID_AA64DFR0_EL1_CTX_CMPS)
+
+#define ID_AA64DFR0_EL1_WRPs_SHIFT UL(20)
+#define ID_AA64DFR0_EL1_WRPs_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_WRPs_MASK MASK(ID_AA64DFR0_EL1_WRPs)
+
+#define ID_AA64DFR0_EL1_BRPs_SHIFT UL(12)
+#define ID_AA64DFR0_EL1_BRPs_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_BRPs_MASK MASK(ID_AA64DFR0_EL1_BRPs)
+
+#define ID_AA64DFR0_EL1_PMUVer_SHIFT UL(8)
+#define ID_AA64DFR0_EL1_PMUVer_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_PMUVer_MASK MASK(ID_AA64DFR0_EL1_PMUVer)
+
+#define ID_AA64DFR0_EL1_TraceVer_SHIFT UL(4)
+#define ID_AA64DFR0_EL1_TraceVer_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_TraceVer_MASK MASK(ID_AA64DFR0_EL1_TraceVer)
+
+#define ID_AA64DFR0_EL1_DebugVer_SHIFT UL(0)
+#define ID_AA64DFR0_EL1_DebugVer_WIDTH UL(4)
+#define ID_AA64DFR0_EL1_DebugVer_MASK MASK(ID_AA64DFR0_EL1_DebugVer)
+
+/* Debug architecture version */
+#define ID_AA64DFR0_EL1_DebugVer_8 UL(6)
+#define ID_AA64DFR0_EL1_DebugVer_8_VHE UL(7)
+#define ID_AA64DFR0_EL1_DebugVer_8_2 UL(8)
+#define ID_AA64DFR0_EL1_DebugVer_8_4 UL(9)
+#define ID_AA64DFR0_EL1_DebugVer_8_8 UL(10)
+
/* ID_AA64PFR0_EL1 definitions */
#define ID_AA64PFR0_EL1_SVE_SHIFT UL(32)
#define ID_AA64PFR0_EL1_SVE_WIDTH UL(4)
@@ -478,8 +538,9 @@
#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 UL(0x2)
/* RNDR definitions */
-#define ID_AA64ISAR0_RNDR_SHIFT UL(60)
-#define ID_AA64ISAR0_RNDR_MASK UL(0xF)
+#define ID_AA64ISAR0_EL1_RNDR_SHIFT UL(60)
+#define ID_AA64ISAR0_EL1_RNDR_WIDTH UL(4)
+#define ID_AA64ISAR0_EL1_RNDR_MASK UL(0xF)
/* ID_AA64MMFR1_EL1 definitions */
#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT UL(4)
@@ -850,10 +911,22 @@
#define ESR_EL2_SYSREG_ID_AA64MMFR1_EL1 SYSREG_ESR(3, 0, 0, 7, 1)
#define ESR_EL2_SYSREG_ID_AA64MMFR2_EL1 SYSREG_ESR(3, 0, 0, 7, 2)
-#define ESR_EL2_SYSREG_ID_AA64ISAR1_GPI_SHIFT 28
-#define ESR_EL2_SYSREG_ID_AA64ISAR1_GPA_SHIFT 24
-#define ESR_EL2_SYSREG_ID_AA64ISAR1_API_SHIFT 8
-#define ESR_EL2_SYSREG_ID_AA64ISAR1_APA_SHIFT 4
+/* ID_AA64ISAR1_EL1 definitions */
+#define ID_AA64ISAR1_EL1_GPI_SHIFT UL(28)
+#define ID_AA64ISAR1_EL1_GPI_WIDTH UL(4)
+#define ID_AA64ISAR1_EL1_GPI_MASK MASK(ID_AA64ISAR1_EL1_GPI)
+
+#define ID_AA64ISAR1_EL1_GPA_SHIFT UL(24)
+#define ID_AA64ISAR1_EL1_GPA_WIDTH UL(4)
+#define ID_AA64ISAR1_EL1_GPA_MASK MASK(ID_AA64ISAR1_EL1_GPA)
+
+#define ID_AA64ISAR1_EL1_API_SHIFT UL(8)
+#define ID_AA64ISAR1_EL1_API_WIDTH UL(4)
+#define ID_AA64ISAR1_EL1_API_MASK MASK(ID_AA64ISAR1_EL1_API)
+
+#define ID_AA64ISAR1_EL1_APA_SHIFT UL(4)
+#define ID_AA64ISAR1_EL1_APA_WIDTH UL(4)
+#define ID_AA64ISAR1_EL1_APA_MASK MASK(ID_AA64ISAR1_EL1_APA)
#define ESR_EL2_SYSREG_TIMERS_MASK SYSREG_ESR(3, 3, 15, 12, 0)
#define ESR_EL2_SYSREG_TIMERS SYSREG_ESR(3, 3, 14, 0, 0)