fix(runtime): Remove hard-coded configuration of VTRC_EL2:PS
The physical address size for the second stage of translation is
currently hard-coded to a maximum of 1TB. That doesn't work for
platforms that have more than 1TB of RAM or with a RAM start address
that is above 1TB.
This patch addresses the issue by making the configuration of
VTRC_EL2:PS based on host machine's physical address range.
Change-Id: If24c1a508054a9bf88d5f6be19c9d5d7f74c99eb
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
diff --git a/lib/arch/include/arch.h b/lib/arch/include/arch.h
index de3b8f7..75a1424 100644
--- a/lib/arch/include/arch.h
+++ b/lib/arch/include/arch.h
@@ -676,7 +676,13 @@
#define VTCR_PS_SHIFT 16
#define VTCR_PS_WIDTH U(3)
+#define VTCR_PS_32 INPLACE(VTCR_PS, UL(0))
+#define VTCR_PS_36 INPLACE(VTCR_PS, UL(1))
#define VTCR_PS_40 INPLACE(VTCR_PS, UL(2))
+#define VTCR_PS_42 INPLACE(VTCR_PS, UL(3))
+#define VTCR_PS_44 INPLACE(VTCR_PS, UL(4))
+#define VTCR_PS_48 INPLACE(VTCR_PS, UL(5))
+#define VTCR_PS_52 INPLACE(VTCR_PS, UL(6))
#define VTCR_VS (UL(1) << 19)
#define VTCR_NSA (UL(1) << 30)
@@ -687,7 +693,6 @@
VTCR_ORGN0_WBRAWA | /* PTW outer cache attr. is WB RAWA*/ \
VTCR_SH0_IS | /* PTW shareability attr. is Outer Sharable*/\
VTCR_TG0_4K | /* 4K granule size in non-secure PT*/ \
- VTCR_PS_40 | /* size(PA) = 40 */ \
/* VS = 0 size(VMID) = 8 */ \
/* NSW = 0 non-secure s2 is made of secure pages*/ \
VTCR_NSA | /* non-secure IPA maps to non-secure PA */ \