fix(mask): remove system registers XXX_MASK definitions
This patch removes XXX_MASK definitions for system registers
bit fields which are replaced by MASK(XXX) macro used directly.
Masking and shifting operations are replaced with
INPLACE() and EXTRACT() macros.
XXX_BIT macros which were defined via INPLACE(XX, 1) are
replaced with (UL(1) << N) definitions, and their XXX_SHIFT
and XXX_WIDTH macros are removed to improve readability
and reduce code size.
This patch also fixes bug in duplicated declaration for
read_ID_AA64MMFR2_EL1() function in arch_helpers.c.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ife64413c45711ba39b043cdc3510cf90fca0cfb6
diff --git a/lib/arch/include/arch_features.h b/lib/arch/include/arch_features.h
index c55e824..23fe6c0 100644
--- a/lib/arch/include/arch_features.h
+++ b/lib/arch/include/arch_features.h
@@ -11,8 +11,8 @@
static inline bool is_armv8_4_ttst_present(void)
{
- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
- ID_AA64MMFR2_EL1_ST_MASK) == 1U;
+ return (EXTRACT(ID_AA64MMFR2_EL1_ST,
+ read_id_aa64mmfr2_el1()) == 1U);
}
/*
@@ -23,8 +23,8 @@
*/
static inline bool is_feat_sve_present(void)
{
- return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SVE_SHIFT) &
- ID_AA64PFR0_EL1_SVE_MASK) != 0UL;
+ return (EXTRACT(ID_AA64PFR0_EL1_SVE,
+ read_id_aa64pfr0_el1()) != 0UL);
}
/*
@@ -32,8 +32,8 @@
*/
static inline bool is_feat_rng_present(void)
{
- return ((read_ID_AA64ISAR0_EL1() >> ID_AA64ISAR0_EL1_RNDR_SHIFT) &
- ID_AA64ISAR0_EL1_RNDR_MASK) != 0UL;
+ return (EXTRACT(ID_AA64ISAR0_EL1_RNDR,
+ read_id_aa64isar0_el1()) != 0UL);
}
/*
@@ -45,9 +45,8 @@
*/
static inline bool is_feat_vmid16_present(void)
{
- return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_VMIDBits_SHIFT) &
- ID_AA64MMFR1_EL1_VMIDBits_MASK) ==
- ID_AA64MMFR1_EL1_VMIDBits_16);
+ return (EXTRACT(ID_AA64MMFR1_EL1_VMIDBits,
+ read_id_aa64mmfr1_el1()) == ID_AA64MMFR1_EL1_VMIDBits_16);
}
/*
@@ -57,11 +56,8 @@
*/
static inline bool is_feat_lpa2_4k_present(void)
{
- u_register_t aa64mmfr0 = read_id_aa64mmfr0_el1();
-
- return ((((aa64mmfr0 >> ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT) &
- ID_AA64MMFR0_EL1_TGRAN4_2_MASK) ==
- ID_AA64MMFR0_EL1_TGRAN4_2_LPA2));
+ return (EXTRACT(ID_AA64MMFR0_EL1_TGRAN4_2,
+ read_id_aa64mmfr0_el1()) == ID_AA64MMFR0_EL1_TGRAN4_2_LPA2);
}
unsigned int arch_feat_get_pa_width(void);