commit 40eea95ff705fe3626d37630a7b0740b4af2978d
author Soby Mathew <soby.mathew@arm.com> Fri Jun 20 15:21:18 2025 +0000
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> Fri Jun 20 15:21:18 2025 +0000
tree 831f46c419d2670866830306707b22471905de8d
parent d1f494756df730c25754d06cfcb462578977cb0b
parent df894df72df41354a65eab61b19c6a41353aa329

Merge "feat(mec): add helper to detect FEAT_MEC presence" into integration

tools/shrinkwrap/configs/rmm-tftf.yaml

diff --git a/tools/shrinkwrap/configs/rmm-tftf.yaml b/tools/shrinkwrap/configs/rmm-tftf.yaml
index 0dad25e..5baad91 100644
--- a/tools/shrinkwrap/configs/rmm-tftf.yaml
+++ b/tools/shrinkwrap/configs/rmm-tftf.yaml
@@ -114,7 +114,36 @@
     # Enable PCIE DOE and IDE
     -C pci.pcie_rc.ahci0.endpoint.doe_supported: 1
     -C pci.pcie_rc.ahci0.endpoint.ide_supported: 1
-
+    -C pci.pcie_rc.ahci0.endpoint.tee_io_supported: 1
+    -C pci.pcie_rc.ahci1.endpoint.doe_supported: 1
+    -C pci.pcie_rc.ahci1.endpoint.ide_supported: 1
+    -C pci.pcie_rc.ahci1.endpoint.tee_io_supported: 1
+    -C pci.pcie_rc.ahci2.endpoint.doe_supported: 1
+    -C pci.pcie_rc.ahci2.endpoint.ide_supported: 1
+    -C pci.pcie_rc.ahci2.endpoint.tee_io_supported: 1
+    -C pci.pcie_rc.rootport0.ide_supported: 1
+    -C pci.pcie_rc.rootport0.tee_io_supported: 1
+    -C pci.pcie_rc.rootport1.ide_supported: 1
+    -C pci.pcie_rc.rootport1.tee_io_supported: 1
+    -C pci.pcie_rc.rootport2.ide_supported: 1
+    -C pci.pcie_rc.rootport2.tee_io_supported: 1
+    -C pci.pcie_rc.rootport3.ide_supported: 1
+    -C pci.pcie_rc.rootport3.tee_io_supported: 1
+    -C pci.pcie_rc.smmuv3testengine0.endpoint.doe_supported: 1
+    -C pci.pcie_rc.smmuv3testengine0.endpoint.ide_supported: 1
+    -C pci.pcie_rc.smmuv3testengine0.endpoint.tee_io_supported: 1
+    -C pci.pcie_rc.ahci0.endpoint.bit_mask_of_base_asym_alg: 4
+    -C pci.pcie_rc.ahci0.endpoint.certificate_der_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/rsa3072/bundle_responder.certchain.der
+    -C pci.pcie_rc.ahci0.endpoint.private_key_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/rsa3072/end_responder.key
+    -C pci.pcie_rc.ahci1.endpoint.bit_mask_of_base_asym_alg: 16
+    -C pci.pcie_rc.ahci1.endpoint.certificate_der_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/ecp256/bundle_responder.certchain.der
+    -C pci.pcie_rc.ahci1.endpoint.private_key_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/ecp256/end_responder.key
+    -C pci.pcie_rc.ahci2.endpoint.bit_mask_of_base_asym_alg: 128
+    -C pci.pcie_rc.ahci2.endpoint.certificate_der_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/ecp384/bundle_responder.certchain.der
+    -C pci.pcie_rc.ahci2.endpoint.private_key_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/ecp384/end_responder.key
+    -C pci.pcie_rc.smmuv3testengine0.endpoint.bit_mask_of_base_asym_alg: 128
+    -C pci.pcie_rc.smmuv3testengine0.endpoint.certificate_der_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/ecp384/bundle_responder.certchain.der
+    -C pci.pcie_rc.smmuv3testengine0.endpoint.private_key_filename: ${btvar:RMM_SRC}/ext/libspdm/unit_test/sample_key/ecp384/end_responder.key
     # Cache modelling settings
     -C cache_state_modelled: ${rtvar:CACHE_MODEL_ENABLED}