chore(lib/arch): rename PA range defines
This patch renames the PARange defines various PA sizes
from Arch defined bit patterns to user readable size based
name.
Change-Id: I17dc23ea24707ae8cf1499d498bd90946e37daff
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
diff --git a/lib/xlat/src/xlat_defs_private.h b/lib/xlat/src/xlat_defs_private.h
index eded9e2..eb574ec 100644
--- a/lib/xlat/src/xlat_defs_private.h
+++ b/lib/xlat/src/xlat_defs_private.h
@@ -95,14 +95,8 @@
#define ATTR_INDEX_MASK U(0x3)
#define ATTR_INDEX_GET(attr) (((attr) >> UL(2)) & ATTR_INDEX_MASK)
-/* Different address masks */
+/* Highest PA address masks */
#define ADDR_MASK_52_TO_63 BIT_MASK_ULL(U(63), U(52))
-#define ADDR_MASK_48_TO_51 BIT_MASK_ULL(U(51), U(48))
-#define ADDR_MASK_44_TO_47 BIT_MASK_ULL(U(47), U(44))
-#define ADDR_MASK_42_TO_43 BIT_MASK_ULL(U(43), U(42))
-#define ADDR_MASK_40_TO_41 BIT_MASK_ULL(U(41), U(40))
-#define ADDR_MASK_36_TO_39 BIT_MASK_ULL(U(39), U(36))
-#define ADDR_MASK_32_TO_35 BIT_MASK_ULL(U(35), U(32))
/*
* Helper function to set the OA into a tte.
diff --git a/lib/xlat/src/xlat_tables_arch.c b/lib/xlat/src/xlat_tables_arch.c
index 5b9215a..a8e9348 100644
--- a/lib/xlat/src/xlat_tables_arch.c
+++ b/lib/xlat/src/xlat_tables_arch.c
@@ -41,44 +41,26 @@
* Encode a Physical Address Space size for its use in TCR_ELx.
* If the PA is not supported, return ULLONG_MAX (~0ULL).
*/
-static uint64_t tcr_physical_addr_size_bits(uintptr_t max_addr)
+static uint64_t tcr_physical_addr_size_bits(unsigned int max_pa_width)
{
- if ((max_addr & ADDR_MASK_52_TO_63) != 0ULL) {
- /* Physical address can't exceed 52 bits */
+ switch (max_pa_width) {
+ case PARANGE_WIDTH_52BITS:
+ return (is_feat_lpa2_4k_present() ? TCR_PS_BITS_4PB : ~(0ULL));
+ case PARANGE_WIDTH_48BITS:
+ return TCR_PS_BITS_256TB;
+ case PARANGE_WIDTH_44BITS:
+ return TCR_PS_BITS_16TB;
+ case PARANGE_WIDTH_42BITS:
+ return TCR_PS_BITS_4TB;
+ case PARANGE_WIDTH_40BITS:
+ return TCR_PS_BITS_1TB;
+ case PARANGE_WIDTH_36BITS:
+ return TCR_PS_BITS_64GB;
+ case PARANGE_WIDTH_32BITS:
+ return TCR_PS_BITS_4GB;
+ default:
return ~(0ULL);
}
-
- /* 52 bits address */
- if ((max_addr & ADDR_MASK_48_TO_51) != 0ULL) {
- return is_feat_lpa2_4k_present() ? TCR_PS_BITS_4PB : ~(0ULL);
- }
-
- /* 48 bits address */
- if ((max_addr & ADDR_MASK_44_TO_47) != 0ULL) {
- return TCR_PS_BITS_256TB;
- }
-
- /* 44 bits address */
- if ((max_addr & ADDR_MASK_42_TO_43) != 0ULL) {
- return TCR_PS_BITS_16TB;
- }
-
- /* 42 bits address */
- if ((max_addr & ADDR_MASK_40_TO_41) != 0ULL) {
- return TCR_PS_BITS_4TB;
- }
-
- /* 40 bits address */
- if ((max_addr & ADDR_MASK_36_TO_39) != 0ULL) {
- return TCR_PS_BITS_1TB;
- }
-
- /* 36 bits address */
- if ((max_addr & ADDR_MASK_32_TO_35) != 0ULL) {
- return TCR_PS_BITS_64GB;
- }
-
- return TCR_PS_BITS_4GB;
}
void xlat_arch_write_mmu_cfg(struct xlat_mmu_cfg *mmu_cfg)
@@ -201,8 +183,7 @@
/*
* Set physical address size to the limit supported by the PE.
*/
- pa_size_bits = tcr_physical_addr_size_bits(
- xlat_arch_get_max_supported_pa());
+ pa_size_bits = tcr_physical_addr_size_bits(arch_feat_get_pa_width());
if (pa_size_bits == ~(0ULL)) {
return -EPERM;
}
diff --git a/lib/xlat/tests/xlat_tests_base_g1.cpp b/lib/xlat/tests/xlat_tests_base_g1.cpp
index 29f5744..b6d1a3d 100644
--- a/lib/xlat/tests/xlat_tests_base_g1.cpp
+++ b/lib/xlat/tests/xlat_tests_base_g1.cpp
@@ -584,10 +584,14 @@
unsigned int index;
uint64_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
bool lpa2 = is_feat_lpa2_4k_present();
- unsigned int pa_range_bits_arr[] = {
- PARANGE_0000_WIDTH, PARANGE_0001_WIDTH, PARANGE_0010_WIDTH,
- PARANGE_0011_WIDTH, PARANGE_0100_WIDTH, PARANGE_0101_WIDTH,
- PARANGE_0110_WIDTH
+ const unsigned int pa_range_bits_arr[] = {
+ [0x0] = PARANGE_WIDTH_32BITS,
+ [0x1] = PARANGE_WIDTH_36BITS,
+ [0x2] = PARANGE_WIDTH_40BITS,
+ [0x3] = PARANGE_WIDTH_42BITS,
+ [0x4] = PARANGE_WIDTH_44BITS,
+ [0x5] = PARANGE_WIDTH_48BITS,
+ [0x6] = PARANGE_WIDTH_52BITS
};
uint64_t max_va_size = XLAT_TEST_MAX_VA_SIZE();
diff --git a/lib/xlat/tests/xlat_tests_base_g2.cpp b/lib/xlat/tests/xlat_tests_base_g2.cpp
index 26e569f..1beb2f9 100644
--- a/lib/xlat/tests/xlat_tests_base_g2.cpp
+++ b/lib/xlat/tests/xlat_tests_base_g2.cpp
@@ -1748,10 +1748,14 @@
uint64_t tte, val_tte;
uint64_t *tbl_ptr;
int base_lvl, end_lvl;
- unsigned int pa_range_bits_arr[] = {
- PARANGE_0000_WIDTH, PARANGE_0001_WIDTH, PARANGE_0010_WIDTH,
- PARANGE_0011_WIDTH, PARANGE_0100_WIDTH, PARANGE_0101_WIDTH,
- PARANGE_0110_WIDTH
+ const unsigned int pa_range_bits_arr[] = {
+ [0x0] = PARANGE_WIDTH_32BITS,
+ [0x1] = PARANGE_WIDTH_36BITS,
+ [0x2] = PARANGE_WIDTH_40BITS,
+ [0x3] = PARANGE_WIDTH_42BITS,
+ [0x4] = PARANGE_WIDTH_44BITS,
+ [0x5] = PARANGE_WIDTH_48BITS,
+ [0x6] = PARANGE_WIDTH_52BITS
};
unsigned int parange_index =
(unsigned int)test_helpers_get_rand_in_range(0UL,
@@ -2143,10 +2147,14 @@
struct xlat_mmap_region init_mmap[2U];
unsigned int pa_index, max_pa_index;
bool lpa2 = is_feat_lpa2_4k_present();
- unsigned int pa_range_bits_arr[] = {
- PARANGE_0000_WIDTH, PARANGE_0001_WIDTH, PARANGE_0010_WIDTH,
- PARANGE_0011_WIDTH, PARANGE_0100_WIDTH, PARANGE_0101_WIDTH,
- PARANGE_0110_WIDTH
+ const unsigned int pa_range_bits_arr[] = {
+ [0x0] = PARANGE_WIDTH_32BITS,
+ [0x1] = PARANGE_WIDTH_36BITS,
+ [0x2] = PARANGE_WIDTH_40BITS,
+ [0x3] = PARANGE_WIDTH_42BITS,
+ [0x4] = PARANGE_WIDTH_44BITS,
+ [0x5] = PARANGE_WIDTH_48BITS,
+ [0x6] = PARANGE_WIDTH_52BITS
};
uint64_t max_va_size = XLAT_TEST_MAX_VA_SIZE();
struct xlat_mmu_cfg mmu_config;