commit 13b86dd3aec91d81290156a6088c1733a1f93d26
author AlexeiFedorov <Alexei.Fedorov@arm.com> Tue Aug 29 10:38:09 2023 +0100
committer Soby Mathew <soby.mathew@arm.com> Tue Sep 05 14:02:41 2023 +0100
tree bbee8730e865bc76c86e94e1aef5952170fc33b2
parent 72bdfded68e266089f229c02ab2bf0d9e06c9c2e

fix(lib/arch): fix MISRA C:2012 Rule 10.1 in sysregs.c

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I1849c040298a4ce232b287c909f6218323c1fe3b

lib/arch/include/arch.h

diff --git a/lib/arch/include/arch.h b/lib/arch/include/arch.h
index a37592a..1e0e6a1 100644
--- a/lib/arch/include/arch.h
+++ b/lib/arch/include/arch.h
@@ -859,11 +859,11 @@
 #define PMSCR_EL2_INIT		0x0
 
 #define SYSREG_ESR(op0, op1, crn, crm, op2) \
-		(((op0) << ESR_EL2_SYSREG_TRAP_OP0_SHIFT) | \
-		 ((op1) << ESR_EL2_SYSREG_TRAP_OP1_SHIFT) | \
-		 ((crn) << ESR_EL2_SYSREG_TRAP_CRN_SHIFT) | \
-		 ((crm) << ESR_EL2_SYSREG_TRAP_CRM_SHIFT) | \
-		 ((op2) << ESR_EL2_SYSREG_TRAP_OP2_SHIFT))
+		((UL(op0) << ESR_EL2_SYSREG_TRAP_OP0_SHIFT) | \
+		 (UL(op1) << ESR_EL2_SYSREG_TRAP_OP1_SHIFT) | \
+		 (UL(crn) << ESR_EL2_SYSREG_TRAP_CRN_SHIFT) | \
+		 (UL(crm) << ESR_EL2_SYSREG_TRAP_CRM_SHIFT) | \
+		 (UL(op2) << ESR_EL2_SYSREG_TRAP_OP2_SHIFT))
 
 #define ESR_EL2_SYSREG_MASK		SYSREG_ESR(3, 7, 15, 15, 7)
 
@@ -924,7 +924,7 @@
 #define ESR_EL2_SYSREG_ICC_SGI0R_EL1		SYSREG_ESR(3, 0, 12, 11, 7)
 
 #define ESR_EL2_SYSREG_DIRECTION	(UL(1) << 0)
-#define ESR_EL2_SYSREG_IS_WRITE(esr)	(!((esr) & ESR_EL2_SYSREG_DIRECTION))
+#define ESR_EL2_SYSREG_IS_WRITE(esr)	(((esr) & ESR_EL2_SYSREG_DIRECTION) == 0UL)
 
 #define ESR_IL(esr)			((esr) & MASK(ESR_EL2_IL))