Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 1 | ###################### |
| 2 | Floating-Point Support |
| 3 | ###################### |
| 4 | |
| 5 | TF-M adds several configuration flags to control Floating point (FP) [1]_ |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 6 | support in TF-M Secure Processing Environment (SPE) and Non Secure Processing |
| 7 | Environment (NSPE). |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 8 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 9 | * Support FP in SPE or NSPE. |
| 10 | * Support FP Application Binary Interface (ABI) [2]_ types: software, hardware. |
| 11 | SPE and NSPE shall use the same FP ABI type. |
| 12 | * Support lazy stacking enable/disable in SPE only, NSPE is not allowed to |
| 13 | enable/disable this feature. |
| 14 | * Support GNU Arm Embedded Toolchain [3]_. ``GNU Arm Embedded Toolchain 10.3- |
| 15 | 2021.10`` and later version shall be used to mitigate VLLDM instruction |
| 16 | security vulnerability [4]_. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 17 | * Support Inter-Process Communication (IPC) [5]_ model in TF-M, and doesn't |
Feder Liang | 98e77a8 | 2021-11-25 14:34:23 +0800 | [diff] [blame] | 18 | support LIBRARY or SFN model. |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 19 | * Support Armv8.0-M mainline. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 20 | * Support isolation level 1,2,3. |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 21 | * Does not support use FPU in First-Level Interrupt Handling (FLIH) [6]_ at |
Feder Liang | 98e77a8 | 2021-11-25 14:34:23 +0800 | [diff] [blame] | 22 | current stage. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 23 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 24 | Please refer to Arm musca S1 [7]_ platform as a reference implementation when |
Feder Liang | 98e77a8 | 2021-11-25 14:34:23 +0800 | [diff] [blame] | 25 | you enable FP support on your platforms. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 26 | |
Lingkai Dong | 181c00c | 2022-04-25 11:36:34 +0100 | [diff] [blame] | 27 | .. Note:: |
| 28 | Alternatively, if you intend to use FP in your own NSPE application but the |
| 29 | TF-M SPE services that you enable do not require FP, you can set the CMake |
| 30 | configuration ``CONFIG_TFM_ENABLE_FPU`` to ``ON`` and **ignore** any |
| 31 | configurations described below. |
| 32 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 33 | ============================ |
| 34 | FP ABI type for SPE and NSPE |
| 35 | ============================ |
| 36 | FP design in Armv8.0-M [8]_ architecture requires consistent FP ABI types |
| 37 | between SPE and NSPE. Furthermore, both sides shall set up CPACR individually |
| 38 | when FPU is used. Otherwise, No Coprocessor (NOCP) usage fault will be asserted |
| 39 | during FP context switch between security states. |
| 40 | |
| 41 | Secure and non-secure libraries are compiled with ``COMPILER_CP_FLAG`` and |
| 42 | linked with ``LINKER_CP_OPTION`` for different FP ABI types. All those |
| 43 | libraries shall be built with ``COMPLIER_CP_FLAG``. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 44 | |
| 45 | If FP ABI types mismatch error is generated during build, pleae check whether |
| 46 | the library is compiled with ``COMPILER_CP_FLAG``. |
| 47 | Example: |
| 48 | |
| 49 | .. code-block:: cmake |
| 50 | |
| 51 | target_compile_options(lib |
| 52 | PRIVATE |
| 53 | ${COMPILER_CP_FLAG} |
| 54 | ) |
| 55 | |
| 56 | =================================== |
| 57 | CMake configurations for FP support |
| 58 | =================================== |
| 59 | The following CMake configurations configure ``COMPILER_CP_FLAG`` in TF-M SPE. |
| 60 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 61 | * ``CONFIG_TFM_FP`` are used to configure FP ABI type for secure and non-secure |
| 62 | side both. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 63 | |
| 64 | +-------------------+---------------------------+ |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 65 | | CONFIG_TFM_FP | FP ABI type [2]_ [3]_ | |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 66 | +===================+===========================+ |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 67 | | soft (default) | Software | |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 68 | +-------------------+---------------------------+ |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 69 | | hard | Hardware | |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 70 | +-------------------+---------------------------+ |
| 71 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 72 | FP software ABI type is default in TF-M. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 73 | |
Lingkai Dong | 181c00c | 2022-04-25 11:36:34 +0100 | [diff] [blame] | 74 | .. Note:: |
| 75 | If you build TF-M SPE with ``CONFIG_TFM_FP=hard`` and provide your own NSPE |
| 76 | application, your own NSPE **must** take care of enabling floating point |
| 77 | coprocessors CP10 and CP11 on the NS side to avoid aforementioned NOCP usage |
| 78 | fault. |
| 79 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 80 | * ``CONFIG_TFM_LAZY_STACKING`` is used to enable/disable lazy stacking |
| 81 | feature. This feature is only valid for FP hardware ABI type. |
| 82 | NSPE is not allowed to enable/disable this feature. Let SPE decide the |
| 83 | secure/non-secure shared setting of lazy stacking to avoid the possible |
| 84 | side-path brought by flexibility. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 85 | |
| 86 | +------------------------------+---------------------------+ |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 87 | | CONFIG_TFM_LAZY_STACKING | Description | |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 88 | +==============================+===========================+ |
| 89 | | 0FF | Disable lazy stacking | |
| 90 | +------------------------------+---------------------------+ |
| 91 | | ON (default) | Enable lazy stacking | |
| 92 | +------------------------------+---------------------------+ |
| 93 | |
| 94 | * ``CONFIG_TFM_FP_ARCH`` specifies which FP architecture is available on the |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 95 | target, valid for FP hardware ABI type. |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 96 | |
| 97 | FP architecture is processor dependent. For GNUARM compiler, example value |
| 98 | are: auto, fpv5-d16, fpv5-sp-d16, etc. |
| 99 | |
| 100 | Default value of ``CONFIG_TFM_FP_ARCH`` for GNUARM compiler is fpv5-sp-d16. |
| 101 | |
| 102 | This parameter shall be specified by platform. Please check compiler |
| 103 | reference manual and processor hardware manual for more details to set |
| 104 | correct FPU configuration for platform. |
| 105 | |
| 106 | |
| 107 | ********* |
| 108 | Reference |
| 109 | ********* |
| 110 | .. [1] `High-Performance Hardware Support for Floating-Point Operations <https://www.arm.com/why-arm/technologies/floating-point>`_ |
| 111 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 112 | .. [2] `Float Point ABI <https://www.keil.com/support/man/docs/armclang_ref/armclang_ref_chr1417451577871.htm>`_ |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 113 | |
| 114 | .. [3] `GNU Arm Embedded Toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm>`_ |
| 115 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 116 | .. [4] `VLLDM instruction Security Vulnerability <https://developer.arm.com/support/arm-security-updates/vlldm-instruction-security-vulnerability>`_ |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 117 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 118 | .. [5] `ArmĀ® Platform Security Architecture Firmware Framework 1.0 <https://armkeil.blob.core.windows.net/developer/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf>`_ |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 119 | |
Anton Komlev | 3356ba3 | 2022-03-31 22:02:11 +0100 | [diff] [blame] | 120 | .. [6] :doc:`Secure Interrupt Integration Guide </integration_guide/tfm_secure_irq_integration_guide>` |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 121 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 122 | .. [7] `Musca-S1 Test Chip Board <https://developer.arm.com/tools-and-software/development-boards/iot-test-chips-and-boards/musca-s1-test-chip-board>`_ |
Feder Liang | 98e77a8 | 2021-11-25 14:34:23 +0800 | [diff] [blame] | 123 | |
Feder Liang | 8ac672f | 2021-12-09 15:03:04 +0800 | [diff] [blame] | 124 | .. [8] `Armv8-M Architecture Reference Manual <https://developer.arm.com/documentation/ddi0553/latest>`_ |
Feder Liang | 4f7c75b | 2021-09-14 16:15:15 +0800 | [diff] [blame] | 125 | |
| 126 | -------------- |
| 127 | |
| 128 | *Copyright (c) 2021, Arm Limited. All rights reserved.* |