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Feder Liang4f7c75b2021-09-14 16:15:15 +08001######################
2Floating-Point Support
3######################
4
5TF-M adds several configuration flags to control Floating point (FP) [1]_
Feder Liang8ac672f2021-12-09 15:03:04 +08006support in TF-M Secure Processing Environment (SPE) and Non Secure Processing
7Environment (NSPE).
Feder Liang4f7c75b2021-09-14 16:15:15 +08008
Feder Liang8ac672f2021-12-09 15:03:04 +08009* Support FP in SPE or NSPE.
10* Support FP Application Binary Interface (ABI) [2]_ types: software, hardware.
11 SPE and NSPE shall use the same FP ABI type.
12* Support lazy stacking enable/disable in SPE only, NSPE is not allowed to
13 enable/disable this feature.
14* Support GNU Arm Embedded Toolchain [3]_. ``GNU Arm Embedded Toolchain 10.3-
15 2021.10`` and later version shall be used to mitigate VLLDM instruction
16 security vulnerability [4]_.
Feder Liang4f7c75b2021-09-14 16:15:15 +080017* Support Inter-Process Communication (IPC) [5]_ model in TF-M, and doesn't
Feder Liang98e77a82021-11-25 14:34:23 +080018 support LIBRARY or SFN model.
Feder Liang8ac672f2021-12-09 15:03:04 +080019* Support Armv8.0-M mainline.
Feder Liang4f7c75b2021-09-14 16:15:15 +080020* Support isolation level 1,2,3.
Feder Liang8ac672f2021-12-09 15:03:04 +080021* Does not support use FPU in First-Level Interrupt Handling (FLIH) [6]_ at
Feder Liang98e77a82021-11-25 14:34:23 +080022 current stage.
Feder Liang4f7c75b2021-09-14 16:15:15 +080023
Feder Liang8ac672f2021-12-09 15:03:04 +080024Please refer to Arm musca S1 [7]_ platform as a reference implementation when
Feder Liang98e77a82021-11-25 14:34:23 +080025you enable FP support on your platforms.
Feder Liang4f7c75b2021-09-14 16:15:15 +080026
Lingkai Dong181c00c2022-04-25 11:36:34 +010027.. Note::
28 Alternatively, if you intend to use FP in your own NSPE application but the
29 TF-M SPE services that you enable do not require FP, you can set the CMake
30 configuration ``CONFIG_TFM_ENABLE_FPU`` to ``ON`` and **ignore** any
31 configurations described below.
32
Feder Liang8ac672f2021-12-09 15:03:04 +080033============================
34FP ABI type for SPE and NSPE
35============================
36FP design in Armv8.0-M [8]_ architecture requires consistent FP ABI types
37between SPE and NSPE. Furthermore, both sides shall set up CPACR individually
38when FPU is used. Otherwise, No Coprocessor (NOCP) usage fault will be asserted
39during FP context switch between security states.
40
41Secure and non-secure libraries are compiled with ``COMPILER_CP_FLAG`` and
42linked with ``LINKER_CP_OPTION`` for different FP ABI types. All those
43libraries shall be built with ``COMPLIER_CP_FLAG``.
Feder Liang4f7c75b2021-09-14 16:15:15 +080044
45If FP ABI types mismatch error is generated during build, pleae check whether
46the library is compiled with ``COMPILER_CP_FLAG``.
47Example:
48
49.. code-block:: cmake
50
51 target_compile_options(lib
52 PRIVATE
53 ${COMPILER_CP_FLAG}
54 )
55
56===================================
57CMake configurations for FP support
58===================================
59The following CMake configurations configure ``COMPILER_CP_FLAG`` in TF-M SPE.
60
Feder Liang8ac672f2021-12-09 15:03:04 +080061* ``CONFIG_TFM_FP`` are used to configure FP ABI type for secure and non-secure
62 side both.
Feder Liang4f7c75b2021-09-14 16:15:15 +080063
64 +-------------------+---------------------------+
Feder Liang8ac672f2021-12-09 15:03:04 +080065 | CONFIG_TFM_FP | FP ABI type [2]_ [3]_ |
Feder Liang4f7c75b2021-09-14 16:15:15 +080066 +===================+===========================+
Feder Liang8ac672f2021-12-09 15:03:04 +080067 | soft (default) | Software |
Feder Liang4f7c75b2021-09-14 16:15:15 +080068 +-------------------+---------------------------+
Feder Liang8ac672f2021-12-09 15:03:04 +080069 | hard | Hardware |
Feder Liang4f7c75b2021-09-14 16:15:15 +080070 +-------------------+---------------------------+
71
Feder Liang8ac672f2021-12-09 15:03:04 +080072 FP software ABI type is default in TF-M.
Feder Liang4f7c75b2021-09-14 16:15:15 +080073
Lingkai Dong181c00c2022-04-25 11:36:34 +010074.. Note::
75 If you build TF-M SPE with ``CONFIG_TFM_FP=hard`` and provide your own NSPE
76 application, your own NSPE **must** take care of enabling floating point
77 coprocessors CP10 and CP11 on the NS side to avoid aforementioned NOCP usage
78 fault.
79
Feder Liang8ac672f2021-12-09 15:03:04 +080080* ``CONFIG_TFM_LAZY_STACKING`` is used to enable/disable lazy stacking
81 feature. This feature is only valid for FP hardware ABI type.
82 NSPE is not allowed to enable/disable this feature. Let SPE decide the
83 secure/non-secure shared setting of lazy stacking to avoid the possible
84 side-path brought by flexibility.
Feder Liang4f7c75b2021-09-14 16:15:15 +080085
86 +------------------------------+---------------------------+
Feder Liang8ac672f2021-12-09 15:03:04 +080087 | CONFIG_TFM_LAZY_STACKING | Description |
Feder Liang4f7c75b2021-09-14 16:15:15 +080088 +==============================+===========================+
89 | 0FF | Disable lazy stacking |
90 +------------------------------+---------------------------+
91 | ON (default) | Enable lazy stacking |
92 +------------------------------+---------------------------+
93
94* ``CONFIG_TFM_FP_ARCH`` specifies which FP architecture is available on the
Feder Liang8ac672f2021-12-09 15:03:04 +080095 target, valid for FP hardware ABI type.
Feder Liang4f7c75b2021-09-14 16:15:15 +080096
97 FP architecture is processor dependent. For GNUARM compiler, example value
98 are: auto, fpv5-d16, fpv5-sp-d16, etc.
99
100 Default value of ``CONFIG_TFM_FP_ARCH`` for GNUARM compiler is fpv5-sp-d16.
101
102 This parameter shall be specified by platform. Please check compiler
103 reference manual and processor hardware manual for more details to set
104 correct FPU configuration for platform.
105
106
107*********
108Reference
109*********
110.. [1] `High-Performance Hardware Support for Floating-Point Operations <https://www.arm.com/why-arm/technologies/floating-point>`_
111
Feder Liang8ac672f2021-12-09 15:03:04 +0800112.. [2] `Float Point ABI <https://www.keil.com/support/man/docs/armclang_ref/armclang_ref_chr1417451577871.htm>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800113
114.. [3] `GNU Arm Embedded Toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm>`_
115
Feder Liang8ac672f2021-12-09 15:03:04 +0800116.. [4] `VLLDM instruction Security Vulnerability <https://developer.arm.com/support/arm-security-updates/vlldm-instruction-security-vulnerability>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800117
Feder Liang8ac672f2021-12-09 15:03:04 +0800118.. [5] `ArmĀ® Platform Security Architecture Firmware Framework 1.0 <https://armkeil.blob.core.windows.net/developer/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800119
Anton Komlev3356ba32022-03-31 22:02:11 +0100120.. [6] :doc:`Secure Interrupt Integration Guide </integration_guide/tfm_secure_irq_integration_guide>`
Feder Liang4f7c75b2021-09-14 16:15:15 +0800121
Feder Liang8ac672f2021-12-09 15:03:04 +0800122.. [7] `Musca-S1 Test Chip Board <https://developer.arm.com/tools-and-software/development-boards/iot-test-chips-and-boards/musca-s1-test-chip-board>`_
Feder Liang98e77a82021-11-25 14:34:23 +0800123
Feder Liang8ac672f2021-12-09 15:03:04 +0800124.. [8] `Armv8-M Architecture Reference Manual <https://developer.arm.com/documentation/ddi0553/latest>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800125
126--------------
127
128*Copyright (c) 2021, Arm Limited. All rights reserved.*