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Feder Liang4f7c75b2021-09-14 16:15:15 +08001######################
2Floating-Point Support
3######################
4
5TF-M adds several configuration flags to control Floating point (FP) [1]_
Feder Liang8ac672f2021-12-09 15:03:04 +08006support in TF-M Secure Processing Environment (SPE) and Non Secure Processing
7Environment (NSPE).
Feder Liang4f7c75b2021-09-14 16:15:15 +08008
Feder Liang8ac672f2021-12-09 15:03:04 +08009* Support FP in SPE or NSPE.
10* Support FP Application Binary Interface (ABI) [2]_ types: software, hardware.
11 SPE and NSPE shall use the same FP ABI type.
12* Support lazy stacking enable/disable in SPE only, NSPE is not allowed to
13 enable/disable this feature.
14* Support GNU Arm Embedded Toolchain [3]_. ``GNU Arm Embedded Toolchain 10.3-
15 2021.10`` and later version shall be used to mitigate VLLDM instruction
16 security vulnerability [4]_.
Xinyu Zhang08cefc12023-11-21 17:12:24 +080017* Support both IPC [5]_ and SFN [11]_ models in TF-M.
Gabor Toth4d414112021-11-10 17:44:50 +010018* Support Armv8-M mainline.
Feder Liang4f7c75b2021-09-14 16:15:15 +080019* Support isolation level 1,2,3.
chesun01305757f2023-02-21 14:19:24 +080020* Support Arm Compiler for Embedded [10]_. ``Arm Compiler for Embedded 6.17``
21 and later version shall be used to mitigate VLLDM instruction security
22 vulnerability [4]_.
Feder Liang8ac672f2021-12-09 15:03:04 +080023* Does not support use FPU in First-Level Interrupt Handling (FLIH) [6]_ at
Feder Liang98e77a82021-11-25 14:34:23 +080024 current stage.
Feder Liang4f7c75b2021-09-14 16:15:15 +080025
Jianliang Shen47d21e52022-08-02 14:36:00 +080026Please refer to Arm AN521 or AN552 platform as a reference implementation when
Feder Liang98e77a82021-11-25 14:34:23 +080027you enable FP support on your platforms.
Feder Liang4f7c75b2021-09-14 16:15:15 +080028
Lingkai Dong181c00c2022-04-25 11:36:34 +010029.. Note::
30 Alternatively, if you intend to use FP in your own NSPE application but the
31 TF-M SPE services that you enable do not require FP, you can set the CMake
Gabor Toth4d414112021-11-10 17:44:50 +010032 configuration ``CONFIG_TFM_ENABLE_CP10CP11`` to ``ON`` and **ignore** any
Lingkai Dong181c00c2022-04-25 11:36:34 +010033 configurations described below.
34
Xinyu Zhang8ec30632022-06-30 18:03:31 +080035.. Note::
Jianliang Shen47d21e52022-08-02 14:36:00 +080036 FPU test issue has not been fixed yet on Musca-S1 [7]_. When running FPU
37 tests on Musca-S1, secure thread fails to trigger secure interrupt. FPU test
38 is disabled by default on Musca-S1 until the issue is fixed.
39
40.. Note::
Xinyu Zhang8ec30632022-06-30 18:03:31 +080041 ``GNU Arm Embedded Toolchain 10.3-2021.10`` may have issue that reports
42 ``'-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main'`` warning [8]_.
43 This issue has been fixed in the later version.
44
Feder Liang8ac672f2021-12-09 15:03:04 +080045============================
46FP ABI type for SPE and NSPE
47============================
Xinyu Zhang8ec30632022-06-30 18:03:31 +080048FP design in Armv8.0-M [9]_ architecture requires consistent FP ABI types
Feder Liang8ac672f2021-12-09 15:03:04 +080049between SPE and NSPE. Furthermore, both sides shall set up CPACR individually
50when FPU is used. Otherwise, No Coprocessor (NOCP) usage fault will be asserted
51during FP context switch between security states.
52
53Secure and non-secure libraries are compiled with ``COMPILER_CP_FLAG`` and
54linked with ``LINKER_CP_OPTION`` for different FP ABI types. All those
55libraries shall be built with ``COMPLIER_CP_FLAG``.
Feder Liang4f7c75b2021-09-14 16:15:15 +080056
57If FP ABI types mismatch error is generated during build, pleae check whether
58the library is compiled with ``COMPILER_CP_FLAG``.
59Example:
60
61.. code-block:: cmake
62
63 target_compile_options(lib
64 PRIVATE
65 ${COMPILER_CP_FLAG}
66 )
67
68===================================
69CMake configurations for FP support
70===================================
71The following CMake configurations configure ``COMPILER_CP_FLAG`` in TF-M SPE.
72
Gabor Toth4d414112021-11-10 17:44:50 +010073* ``CONFIG_TFM_ENABLE_FP`` is used to enable/disable FPU usage.
Feder Liang4f7c75b2021-09-14 16:15:15 +080074
Gabor Toth4d414112021-11-10 17:44:50 +010075 +--------------------------+---------------------------+
76 | CONFIG_TFM_ENABLE_FP | FP support |
77 +==========================+===========================+
chesun01305757f2023-02-21 14:19:24 +080078 | off (default) | FP disabled |
Gabor Toth4d414112021-11-10 17:44:50 +010079 +--------------------------+---------------------------+
80 | on | FP enabled |
81 +--------------------------+---------------------------+
Feder Liang4f7c75b2021-09-14 16:15:15 +080082
Lingkai Dong181c00c2022-04-25 11:36:34 +010083.. Note::
Gabor Toth4d414112021-11-10 17:44:50 +010084 ``CONFIG_TFM_FLOAT_ABI`` depends on ``CONFIG_TFM_ENABLE_FP``. If
85 ``CONFIG_TFM_ENABLE_FP is set ``CONFIG_TFM_FLOAT_ABI`` is automatically
86 set to ``hard``.
87
88.. Note::
89 If you build TF-M SPE with ``CONFIG_TFM_ENABLE_FP=on`` and provide your own
90 NSPE application, your own NSPE **must** take care of enabling floating point
Lingkai Dong181c00c2022-04-25 11:36:34 +010091 coprocessors CP10 and CP11 on the NS side to avoid aforementioned NOCP usage
92 fault.
93
Feder Liang8ac672f2021-12-09 15:03:04 +080094* ``CONFIG_TFM_LAZY_STACKING`` is used to enable/disable lazy stacking
95 feature. This feature is only valid for FP hardware ABI type.
96 NSPE is not allowed to enable/disable this feature. Let SPE decide the
97 secure/non-secure shared setting of lazy stacking to avoid the possible
98 side-path brought by flexibility.
Feder Liang4f7c75b2021-09-14 16:15:15 +080099
100 +------------------------------+---------------------------+
Feder Liang8ac672f2021-12-09 15:03:04 +0800101 | CONFIG_TFM_LAZY_STACKING | Description |
Feder Liang4f7c75b2021-09-14 16:15:15 +0800102 +==============================+===========================+
103 | 0FF | Disable lazy stacking |
104 +------------------------------+---------------------------+
105 | ON (default) | Enable lazy stacking |
106 +------------------------------+---------------------------+
107
108* ``CONFIG_TFM_FP_ARCH`` specifies which FP architecture is available on the
Feder Liang8ac672f2021-12-09 15:03:04 +0800109 target, valid for FP hardware ABI type.
Feder Liang4f7c75b2021-09-14 16:15:15 +0800110
111 FP architecture is processor dependent. For GNUARM compiler, example value
chesun01305757f2023-02-21 14:19:24 +0800112 are: auto, fpv5-d16, fpv5-sp-d16, etc. For armclang, example value are: none,
113 softvfp, fpv5-d16, fpv5-sp-d16, etc.
Feder Liang4f7c75b2021-09-14 16:15:15 +0800114
Joakim Andersson92309262023-02-08 14:41:14 +0100115 This parameter shall be specified by platform in preload.cmake. Please check
116 compiler reference manual and processor hardware manual for more details to
117 set correct FPU configuration for platform.
Feder Liang4f7c75b2021-09-14 16:15:15 +0800118
chesun01305757f2023-02-21 14:19:24 +0800119* ``CONFIG_TFM_FP_ARCH_ASM`` specifies the target FPU architecture name shared
120 by Arm Compiler armasm and armlink. It is only used in the ``--fpu=`` argument
121 by Arm Compiler and shall be aligned with ``CONFIG_TFM_FP_ARCH``.
122
123 FP architecture is processor dependent. For armasm and armlink, example value
124 are: SoftVFP, FPv5_D16, etc.
125
126 This parameter shall be specified by platform in preload.cmake. Please check
127 compiler reference manual and processor hardware manual for more details to
128 set correct FPU configuration for platform.
Feder Liang4f7c75b2021-09-14 16:15:15 +0800129
130*********
131Reference
132*********
133.. [1] `High-Performance Hardware Support for Floating-Point Operations <https://www.arm.com/why-arm/technologies/floating-point>`_
134
Feder Liang8ac672f2021-12-09 15:03:04 +0800135.. [2] `Float Point ABI <https://www.keil.com/support/man/docs/armclang_ref/armclang_ref_chr1417451577871.htm>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800136
137.. [3] `GNU Arm Embedded Toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm>`_
138
Feder Liang8ac672f2021-12-09 15:03:04 +0800139.. [4] `VLLDM instruction Security Vulnerability <https://developer.arm.com/support/arm-security-updates/vlldm-instruction-security-vulnerability>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800140
Elena Uziunaite66461ae2023-11-10 16:51:59 +0000141.. [5] `ArmĀ® Platform Security Architecture Firmware Framework 1.0 <https://developer.arm.com/documentation/den0063/latest/>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800142
Anton Komlev3356ba32022-03-31 22:02:11 +0100143.. [6] :doc:`Secure Interrupt Integration Guide </integration_guide/tfm_secure_irq_integration_guide>`
Feder Liang4f7c75b2021-09-14 16:15:15 +0800144
Feder Liang8ac672f2021-12-09 15:03:04 +0800145.. [7] `Musca-S1 Test Chip Board <https://developer.arm.com/tools-and-software/development-boards/iot-test-chips-and-boards/musca-s1-test-chip-board>`_
Feder Liang98e77a82021-11-25 14:34:23 +0800146
Xinyu Zhang8ec30632022-06-30 18:03:31 +0800147.. [8] `GCC Issue on '-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main' Warning <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97327>`_
148
149.. [9] `Armv8-M Architecture Reference Manual <https://developer.arm.com/documentation/ddi0553/latest>`_
Feder Liang4f7c75b2021-09-14 16:15:15 +0800150
chesun01305757f2023-02-21 14:19:24 +0800151.. [10] `Arm Compiler for Embedded <https://developer.arm.com/Tools%20and%20Software/Arm%20Compiler%20for%20Embedded>`_
152
Xinyu Zhang08cefc12023-11-21 17:12:24 +0800153.. [11] `FF-M v1.1 Extension <https://developer.arm.com/documentation/aes0039/latest/>`__
154
Feder Liang4f7c75b2021-09-14 16:15:15 +0800155--------------
156
Xinyu Zhang08cefc12023-11-21 17:12:24 +0800157*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*