Functions | |
| __STATIC_INLINE uint8_t | Cy_SmartIO_GetChBypass (SMARTIO_PRT_Type *base) |
| Gets the bypass/route state of all 8 channels in the Smart I/O. More... | |
| cy_en_smartio_status_t | Cy_SmartIO_SetChBypass (SMARTIO_PRT_Type *base, uint8_t bypassMask) |
| Sets the bypass/route state of all 8 channels in the Smart I/O. More... | |
| __STATIC_INLINE cy_en_smartio_clksrc_t | Cy_SmartIO_GetClock (SMARTIO_PRT_Type *base) |
| Gets the clock source of the Smart I/O. More... | |
| cy_en_smartio_status_t | Cy_SmartIO_SetClock (SMARTIO_PRT_Type *base, cy_en_smartio_clksrc_t clkSrc) |
| Sets the clock source of the Smart I/O. More... | |
| __STATIC_INLINE uint8_t | Cy_SmartIO_GetIoSync (SMARTIO_PRT_Type *base) |
| Gets the synchronization mode of the 8 I/O terminals. More... | |
| cy_en_smartio_status_t | Cy_SmartIO_SetIoSync (SMARTIO_PRT_Type *base, uint8_t ioSyncEn) |
| Sets the synchronization mode of the 8 I/O terminals. More... | |
| __STATIC_INLINE uint8_t | Cy_SmartIO_GetChipSync (SMARTIO_PRT_Type *base) |
| Gets the synchronization mode of the 8 chip-side terminals. More... | |
| cy_en_smartio_status_t | Cy_SmartIO_SetChipSync (SMARTIO_PRT_Type *base, uint8_t chipSyncEn) |
| Sets the synchronization mode of the 8 chip-side terminals. More... | |
| cy_en_smartio_status_t | Cy_SmartIO_HoldOverride (SMARTIO_PRT_Type *base, bool hldOvr) |
| Configures the hold override mode. More... | |
| __STATIC_INLINE uint8_t Cy_SmartIO_GetChBypass | ( | SMARTIO_PRT_Type * | base | ) |
Gets the bypass/route state of all 8 channels in the Smart I/O.
| Bypass bit | Channel |
|---|---|
| 0 | io0<->chip0 |
| 1 | io1<->chip1 |
| 2 | io2<->chip2 |
| 3 | io3<->chip3 |
| 4 | io4<->chip4 |
| 5 | io5<->chip5 |
| 6 | io6<->chip6 |
| 7 | io7<->chip7 |
| base | Pointer to the Smart I/O base address |
| cy_en_smartio_status_t Cy_SmartIO_SetChBypass | ( | SMARTIO_PRT_Type * | base, |
| uint8_t | bypassMask | ||
| ) |
Sets the bypass/route state of all 8 channels in the Smart I/O.
| Bypass bit | Channel |
|---|---|
| 0 | io0<->chip0 |
| 1 | io1<->chip1 |
| 2 | io2<->chip2 |
| 3 | io3<->chip3 |
| 4 | io4<->chip4 |
| 5 | io5<->chip5 |
| 6 | io6<->chip6 |
| 7 | io7<->chip7 |
| base | Pointer to the Smart I/O base address |
| bypassMask | Bypass/Route state of 8 io<->chip channels (bits [7:0]): 1=bypass, 0=routed. |
| __STATIC_INLINE cy_en_smartio_clksrc_t Cy_SmartIO_GetClock | ( | SMARTIO_PRT_Type * | base | ) |
Gets the clock source of the Smart I/O.
| base | Pointer to the Smart I/O base address |
| cy_en_smartio_status_t Cy_SmartIO_SetClock | ( | SMARTIO_PRT_Type * | base, |
| cy_en_smartio_clksrc_t | clkSrc | ||
| ) |
Sets the clock source of the Smart I/O.
| base | Pointer to the Smart I/O base address |
| clkSrc | Pointer to the Smart I/O base address |
| __STATIC_INLINE uint8_t Cy_SmartIO_GetIoSync | ( | SMARTIO_PRT_Type * | base | ) |
Gets the synchronization mode of the 8 I/O terminals.
| Sync bit | I/O terminal |
|---|---|
| 0 | io0 |
| 1 | io1 |
| 2 | io2 |
| 3 | io3 |
| 4 | io4 |
| 5 | io5 |
| 6 | io6 |
| 7 | io7 |
| base | Pointer to the Smart I/O base address |
| cy_en_smartio_status_t Cy_SmartIO_SetIoSync | ( | SMARTIO_PRT_Type * | base, |
| uint8_t | ioSyncEn | ||
| ) |
Sets the synchronization mode of the 8 I/O terminals.
| Sync bit | I/O terminal |
|---|---|
| 0 | io0 |
| 1 | io1 |
| 2 | io2 |
| 3 | io3 |
| 4 | io4 |
| 5 | io5 |
| 6 | io6 |
| 7 | io7 |
| base | Pointer to the Smart I/O base address |
| ioSyncEn | Sync mode of 8 I/O terminals (bits [7:0]): 1=sync, 0=no sync. |
| __STATIC_INLINE uint8_t Cy_SmartIO_GetChipSync | ( | SMARTIO_PRT_Type * | base | ) |
Gets the synchronization mode of the 8 chip-side terminals.
| Sync bit | chip terminal |
|---|---|
| 0 | chip0 |
| 1 | chip1 |
| 2 | chip2 |
| 3 | chip3 |
| 4 | chip4 |
| 5 | chip5 |
| 6 | chip6 |
| 7 | chip7 |
| base | Pointer to the Smart I/O base address |
| cy_en_smartio_status_t Cy_SmartIO_SetChipSync | ( | SMARTIO_PRT_Type * | base, |
| uint8_t | chipSyncEn | ||
| ) |
Sets the synchronization mode of the 8 chip-side terminals.
| Sync bit | chip terminal |
|---|---|
| 0 | chip0 |
| 1 | chip1 |
| 2 | chip2 |
| 3 | chip3 |
| 4 | chip4 |
| 5 | chip5 |
| 6 | chip6 |
| 7 | chip7 |
| base | Pointer to the Smart I/O base address |
| chipSyncEn | Sync mode of 8 chip-side terminals (bits [7:0]): 1=sync, 0=no sync. |
| cy_en_smartio_status_t Cy_SmartIO_HoldOverride | ( | SMARTIO_PRT_Type * | base, |
| bool | hldOvr | ||
| ) |
Configures the hold override mode.
In Deep-Sleep power mode, the HSIOM holds the GPIO output and output enable signals for all signals that operate in chip active domain. Enabling the hold override allows the Smart I/O to deliver Deep-Sleep output functionality on these GPIO terminals. If the Smart I/O should not drive any of the GPIO outputs, the hold override should be disabled.
| base | Pointer to the Smart I/O base address |
| hldOvr | true = Enabled: Smart I/O controls the port I/Os false = Disabled: HSIOM controls the port I/Os |