Build: Major warnings cleanup
This is a major type-mismatch cleanup and warnings elimination.
The IAR toolchain runs with more warnings enabled than ARMCLANG or
GNUARM, which has resulted in this effort.
This should make it easier to enable "pedantic" mode also for GNUARM.
There are still a few warnings about jumping past variable
initialization and falling off the end of non-void functions, but there
are comments in some of these parts that implies that this is done to
catch programming errors, like having case labels for all possible enum
values.
Reordered initializer in tfm_attestation_req_mngr.c to eliminate CI
warning.
Disabled "Pe940" warnings in CommonConfig.cmake to suppress warnings
about inline assembly functions declared to return value that doesn't
declare a return value in the __ASM() statement.
Disabled "Pe546" warnings to supress warnings about jumping over
unused initializers.
Fixed what appears to be a copy/paste bug in tfm_ss_core_test.c.
Removed unused variable "ret" in Driver_PPC.c for AN519 and AN521, to
make it similar to AN524.
Signed-off-by: TTornblom <thomas.tornblom@iar.com>
Change-Id: I2b729c73e4b004cff6b0530cc1350fcf900e4272
diff --git a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c
index 4890afb..6ddb7c5 100644
--- a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c
+++ b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Driver_USART.c
@@ -207,7 +207,7 @@
return uart_dev->rx_nbr_bytes;
}
-static uint32_t USARTx_SetDataBits(uint32_t control,
+static int32_t USARTx_SetDataBits(uint32_t control,
cy_stc_scb_uart_config_t *config)
{
switch (control & ARM_USART_DATA_BITS_Msk) {
@@ -238,7 +238,7 @@
return ARM_DRIVER_OK;
}
-static uint32_t USARTx_SetParity(uint32_t control,
+static int32_t USARTx_SetParity(uint32_t control,
cy_stc_scb_uart_config_t *config)
{
switch (control & ARM_USART_PARITY_Msk) {
@@ -261,7 +261,7 @@
return ARM_DRIVER_OK;
}
-static uint32_t USARTx_SetStopBits(uint32_t control,
+static int32_t USARTx_SetStopBits(uint32_t control,
cy_stc_scb_uart_config_t *config)
{
switch (control & ARM_USART_STOP_BITS_Msk) {
diff --git a/platform/ext/target/cypress/psoc64/smpu_config.h b/platform/ext/target/cypress/psoc64/smpu_config.h
index 236fc67..c6df71a 100644
--- a/platform/ext/target/cypress/psoc64/smpu_config.h
+++ b/platform/ext/target/cypress/psoc64/smpu_config.h
@@ -47,7 +47,7 @@
CY_PROT_SUBREGION_DIS7)
#define SMPU0_SLAVE_CONFIG {\
.address = (void *)SMPU0_BASE, \
- .regionSize = SMPU0_REGIONSIZE, \
+ .regionSize = (cy_en_prot_size_t) SMPU0_REGIONSIZE, \
.subregions = SMPU0_SUBREGION_DIS, \
.userPermission = CY_PROT_PERM_RWX, \
.privPermission = CY_PROT_PERM_RWX, \
@@ -74,7 +74,7 @@
#define SMPU1_REGIONSIZE PROT_SIZE_16KB_BIT_SHIFT
#define SMPU1_SLAVE_CONFIG {\
.address = (void *)SMPU1_BASE, \
- .regionSize = SMPU1_REGIONSIZE, \
+ .regionSize = (cy_en_prot_size_t) SMPU1_REGIONSIZE, \
.subregions = ALL_ENABLED, \
.userPermission = CY_PROT_PERM_RW, \
.privPermission = CY_PROT_PERM_RW, \
@@ -99,7 +99,7 @@
#define SMPU2_REGIONSIZE PROT_SIZE_512B_BIT_SHIFT
#define SMPU2_SLAVE_CONFIG {\
.address = (void *)SMPU2_BASE, \
- .regionSize = SMPU2_REGIONSIZE, \
+ .regionSize = (cy_en_prot_size_t) SMPU2_REGIONSIZE, \
.subregions = ALL_ENABLED, \
.userPermission = CY_PROT_PERM_RW, \
.privPermission = CY_PROT_PERM_RW, \
@@ -127,7 +127,7 @@
CY_PROT_SUBREGION_DIS2)
#define SMPU3_SLAVE_CONFIG {\
.address = (void *)SMPU3_BASE, \
- .regionSize = SMPU3_REGIONSIZE, \
+ .regionSize = (cy_en_prot_size_t) SMPU3_REGIONSIZE, \
.subregions = SMPU3_SUBREGION_DIS, \
.userPermission = CY_PROT_PERM_RW, \
.privPermission = CY_PROT_PERM_RW, \
@@ -161,7 +161,7 @@
#define SMPU6_REGIONSIZE PROT_SIZE_32KB_BIT_SHIFT
#define SMPU6_SLAVE_CONFIG {\
.address = (void *)SMPU6_BASE, \
- .regionSize = SMPU6_REGIONSIZE, \
+ .regionSize = (cy_en_prot_size_t) SMPU6_REGIONSIZE, \
.subregions = ALL_ENABLED, \
.userPermission = CY_PROT_PERM_RW, \
.privPermission = CY_PROT_PERM_RW, \
@@ -188,7 +188,7 @@
CY_PROT_SUBREGION_DIS1)
#define SMPU7_SLAVE_CONFIG {\
.address = (void *)SMPU7_BASE, \
- .regionSize = SMPU7_REGIONSIZE, \
+ .regionSize = (cy_en_prot_size_t) SMPU7_REGIONSIZE, \
.subregions = SMPU7_SUBREGION_DIS, \
.userPermission = CY_PROT_PERM_DISABLED, \
.privPermission = CY_PROT_PERM_RW, \
diff --git a/platform/ext/target/cypress/psoc64/spm_hal.c b/platform/ext/target/cypress/psoc64/spm_hal.c
index 62dc8a7..f181c1f 100644
--- a/platform/ext/target/cypress/psoc64/spm_hal.c
+++ b/platform/ext/target/cypress/psoc64/spm_hal.c
@@ -244,7 +244,7 @@
IPC_TX_NOTIFY_MASK, IPC_SYNC_MAGIC);
while (1)
{
- status = Cy_IPC_Drv_GetInterruptStatusMasked(
+ status = (cy_en_ipcdrv_status_t) Cy_IPC_Drv_GetInterruptStatusMasked(
Cy_IPC_Drv_GetIntrBaseAddr(IPC_RX_INTR_STRUCT));
status >>= CY_IPC_NOTIFY_SHIFT;
if (status & IPC_RX_INT_MASK) {
@@ -267,7 +267,7 @@
}
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -345,23 +345,23 @@
return nvic_interrupt_enable();
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
(void)irq_line;
diff --git a/platform/ext/target/cypress/psoc64/target_cfg.c b/platform/ext/target/cypress/psoc64/target_cfg.c
index 99c341e..9014a35 100644
--- a/platform/ext/target/cypress/psoc64/target_cfg.c
+++ b/platform/ext/target/cypress/psoc64/target_cfg.c
@@ -1184,14 +1184,11 @@
void ppu_init_cfg(void)
{
- cy_en_prot_status_t ret;
- (void)ret;
-
size_t n = sizeof(ppu_init_table)/sizeof(ppu_init_table[0]);
for (int i = 0; i < n; i++)
{
- ret = PPU_Configure(ppu_init_table[i]);
+ cy_en_prot_status_t ret = PPU_Configure(ppu_init_table[i]);
assert(ret == CY_PROT_SUCCESS);
}
diff --git a/platform/ext/target/mps2/an519/cmsis_drivers/Driver_PPC.c b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_PPC.c
index 9787d05..fc198a2 100644
--- a/platform/ext/target/mps2/an519/cmsis_drivers/Driver_PPC.c
+++ b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_PPC.c
@@ -734,11 +734,9 @@
ARM_PPC_SecAttr sec_attr,
ARM_PPC_PrivAttr priv_attr)
{
- enum ppc_sse200_error_t ret;
-
- ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV_S, periph,
- (enum ppc_sse200_sec_attr_t)sec_attr,
- (enum ppc_sse200_priv_attr_t)priv_attr);
+ ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
return ARM_DRIVER_OK;
}
diff --git a/platform/ext/target/mps2/an519/spm_hal.c b/platform/ext/target/mps2/an519/spm_hal.c
index 22f8758..8d0514d 100644
--- a/platform/ext/target/mps2/an519/spm_hal.c
+++ b/platform/ext/target/mps2/an519/spm_hal.c
@@ -228,7 +228,7 @@
return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -236,23 +236,23 @@
return TFM_PLAT_ERR_SUCCESS;
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
diff --git a/platform/ext/target/mps2/an519/target_cfg.h b/platform/ext/target/mps2/an519/target_cfg.h
index e31971e..fb985bf 100644
--- a/platform/ext/target/mps2/an519/target_cfg.h
+++ b/platform/ext/target/mps2/an519/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited
+ * Copyright (c) 2017-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -72,7 +72,7 @@
{
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/ext/target/mps2/an521/cmsis_drivers/Driver_PPC.c b/platform/ext/target/mps2/an521/cmsis_drivers/Driver_PPC.c
index 9787d05..fc198a2 100644
--- a/platform/ext/target/mps2/an521/cmsis_drivers/Driver_PPC.c
+++ b/platform/ext/target/mps2/an521/cmsis_drivers/Driver_PPC.c
@@ -734,11 +734,9 @@
ARM_PPC_SecAttr sec_attr,
ARM_PPC_PrivAttr priv_attr)
{
- enum ppc_sse200_error_t ret;
-
- ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV_S, periph,
- (enum ppc_sse200_sec_attr_t)sec_attr,
- (enum ppc_sse200_priv_attr_t)priv_attr);
+ ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
return ARM_DRIVER_OK;
}
diff --git a/platform/ext/target/mps2/an521/spm_hal.c b/platform/ext/target/mps2/an521/spm_hal.c
index 6526e31..51d488b 100644
--- a/platform/ext/target/mps2/an521/spm_hal.c
+++ b/platform/ext/target/mps2/an521/spm_hal.c
@@ -261,7 +261,7 @@
return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -269,23 +269,23 @@
return TFM_PLAT_ERR_SUCCESS;
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
diff --git a/platform/ext/target/mps2/an521/target_cfg.h b/platform/ext/target/mps2/an521/target_cfg.h
index e31971e..fb985bf 100644
--- a/platform/ext/target/mps2/an521/target_cfg.h
+++ b/platform/ext/target/mps2/an521/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited
+ * Copyright (c) 2017-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -72,7 +72,7 @@
{
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/ext/target/mps2/an539/spm_hal.c b/platform/ext/target/mps2/an539/spm_hal.c
index ce345c5..93f0a93 100644
--- a/platform/ext/target/mps2/an539/spm_hal.c
+++ b/platform/ext/target/mps2/an539/spm_hal.c
@@ -242,7 +242,7 @@
return *((uint32_t *)(memory_regions.non_secure_code_start + 4));
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line, uint32_t priority)
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line, uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
NVIC_SetPriority(irq_line, quantized_priority);
@@ -291,7 +291,7 @@
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
@@ -329,17 +329,17 @@
return nvic_interrupt_enable();
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
diff --git a/platform/ext/target/mps2/an539/target_cfg.h b/platform/ext/target/mps2/an539/target_cfg.h
index 7667485..c92c488 100644
--- a/platform/ext/target/mps2/an539/target_cfg.h
+++ b/platform/ext/target/mps2/an539/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -59,7 +59,7 @@
struct tfm_spm_partition_platform_data_t {
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/ext/target/mps3/an524/cmsis_drivers/Driver_PPC.c b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_PPC.c
index a17e157..9ffc35f 100644
--- a/platform/ext/target/mps3/an524/cmsis_drivers/Driver_PPC.c
+++ b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_PPC.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2016-2020 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -817,11 +817,9 @@
ARM_PPC_SecAttr sec_attr,
ARM_PPC_PrivAttr priv_attr)
{
- enum ppc_sse200_error_t ret;
-
- ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV, periph,
- (enum ppc_sse200_sec_attr_t)sec_attr,
- (enum ppc_sse200_priv_attr_t)priv_attr);
+ ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
return ARM_DRIVER_OK;
}
diff --git a/platform/ext/target/mps3/an524/spm_hal.c b/platform/ext/target/mps3/an524/spm_hal.c
index c39c2ca..f5dd600 100644
--- a/platform/ext/target/mps3/an524/spm_hal.c
+++ b/platform/ext/target/mps3/an524/spm_hal.c
@@ -275,7 +275,7 @@
return TFM_PLAT_ERR_SUCCESS;
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -283,23 +283,23 @@
return TFM_PLAT_ERR_SUCCESS;
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
diff --git a/platform/ext/target/mps3/an524/target_cfg.c b/platform/ext/target/mps3/an524/target_cfg.c
index 11b6884..cdc3fee 100644
--- a/platform/ext/target/mps3/an524/target_cfg.c
+++ b/platform/ext/target/mps3/an524/target_cfg.c
@@ -257,7 +257,7 @@
NVIC_EnableIRQ(PPC_IRQn);
- return ARM_DRIVER_OK;
+ return (enum tfm_plat_err_t) ARM_DRIVER_OK;
}
/*------------------- SAU/IDAU configuration functions -----------------------*/
diff --git a/platform/ext/target/mps3/an524/target_cfg.h b/platform/ext/target/mps3/an524/target_cfg.h
index 715e79a..6cc3ed1 100644
--- a/platform/ext/target/mps3/an524/target_cfg.h
+++ b/platform/ext/target/mps3/an524/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -60,7 +60,7 @@
struct tfm_spm_partition_platform_data_t {
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
index b29f03f..d8c23b3 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -249,8 +249,8 @@
/* The erase function checks whether the address is aligned with
* the sector or subsector and checks the Flash memory boundaries.
*/
- err = mt25ql_erase(ARM_FLASH0_DEV.dev,
- addr, ARM_FLASH0_DEV.data->sector_size);
+ err = mt25ql_erase(ARM_FLASH0_DEV.dev, addr,
+ (enum mt25ql_erase_t) ARM_FLASH0_DEV.data->sector_size);
ARM_FLASH0_STATUS.busy = DRIVER_STATUS_IDLE;
diff --git a/platform/ext/target/musca_a/Device/Source/device_definition.c b/platform/ext/target/musca_a/Device/Source/device_definition.c
index 43913d4..1773e08 100644
--- a/platform/ext/target/musca_a/Device/Source/device_definition.c
+++ b/platform/ext/target/musca_a/Device/Source/device_definition.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -615,7 +615,7 @@
* more.
*/
.size = 0x00800000U, /* 8 MiB */
- .config_state = { 0 },
+ .config_state = { MT25QL_FUNC_STATE_NOT_INITED },
};
#endif
@@ -632,6 +632,6 @@
* more.
*/
.size = 0x00800000U, /* 8 MiB */
- .config_state = { 0 },
+ .config_state = { MT25QL_FUNC_STATE_NOT_INITED },
};
#endif
diff --git a/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c b/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c
index 578cc5b..f748ecf 100644
--- a/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c
+++ b/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited
+ * Copyright (c) 2018-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -514,7 +514,7 @@
qspi_ip6514e_enable(dev->controller);
- dev->config_state = (struct mt25ql_config_state_t){ 0 };
+ dev->config_state = (struct mt25ql_config_state_t){ MT25QL_FUNC_STATE_NOT_INITED };
dev->config_state.func_state = MT25QL_FUNC_STATE_NOT_INITED;
return MT25QL_ERR_NONE;
diff --git a/platform/ext/target/musca_a/services/src/tfm_ioctl_s_api.c b/platform/ext/target/musca_a/services/src/tfm_ioctl_s_api.c
index e734f12..e744f39 100644
--- a/platform/ext/target/musca_a/services/src/tfm_ioctl_s_api.c
+++ b/platform/ext/target/musca_a/services/src/tfm_ioctl_s_api.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -31,7 +31,7 @@
&out_vec);
*result = out.u.result;
- return ret;
+ return (enum tfm_platform_err_t) ret;
}
__attribute__((section("SFN")))
@@ -60,7 +60,7 @@
&out_vec);
*result = out.u.result;
- return ret;
+ return (enum tfm_platform_err_t) ret;
}
__attribute__((section("SFN")))
@@ -88,7 +88,7 @@
&out_vec);
*result = out.u.result;
- return ret;
+ return (enum tfm_platform_err_t) ret;
}
__attribute__((section("SFN")))
@@ -116,7 +116,7 @@
*result = out.u.gpio_read_result.result;
*data = out.u.gpio_read_result.data;
- return ret;
+ return (enum tfm_platform_err_t) ret;
}
__attribute__((section("SFN")))
@@ -145,7 +145,7 @@
&out_vec);
*result = out.u.result;
- return ret;
+ return (enum tfm_platform_err_t) ret;
}
__attribute__((section("SFN")))
@@ -174,7 +174,7 @@
&out_vec);
*result = out.u.result;
- return ret;
+ return (enum tfm_platform_err_t) ret;
}
__attribute__((section("SFN")))
@@ -202,6 +202,6 @@
*result = out.u.gpio_read_result.result;
*data = out.u.gpio_read_result.data;
- return ret;
+ return (enum tfm_platform_err_t) ret;
}
diff --git a/platform/ext/target/musca_a/spm_hal.c b/platform/ext/target/musca_a/spm_hal.c
index 36f1e15..b361d73 100644
--- a/platform/ext/target/musca_a/spm_hal.c
+++ b/platform/ext/target/musca_a/spm_hal.c
@@ -268,7 +268,7 @@
return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -276,23 +276,23 @@
return TFM_PLAT_ERR_SUCCESS;
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
diff --git a/platform/ext/target/musca_a/target_cfg.h b/platform/ext/target/musca_a/target_cfg.h
index 742fab6..dfbed39 100644
--- a/platform/ext/target/musca_a/target_cfg.h
+++ b/platform/ext/target/musca_a/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited
+ * Copyright (c) 2018-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -67,7 +67,7 @@
{
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/ext/target/musca_b1/spm_hal.c b/platform/ext/target/musca_b1/spm_hal.c
index d9ae389..11c4af9 100644
--- a/platform/ext/target/musca_b1/spm_hal.c
+++ b/platform/ext/target/musca_b1/spm_hal.c
@@ -287,7 +287,7 @@
return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -295,23 +295,23 @@
return TFM_PLAT_ERR_SUCCESS;
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
diff --git a/platform/ext/target/musca_b1/target_cfg.h b/platform/ext/target/musca_b1/target_cfg.h
index 26f2968..c6bb82d 100644
--- a/platform/ext/target/musca_b1/target_cfg.h
+++ b/platform/ext/target/musca_b1/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited
+ * Copyright (c) 2018-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -75,7 +75,7 @@
{
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/ext/target/musca_s1/spm_hal.c b/platform/ext/target/musca_s1/spm_hal.c
index 45622c4..741dc58 100644
--- a/platform/ext/target/musca_s1/spm_hal.c
+++ b/platform/ext/target/musca_s1/spm_hal.c
@@ -237,7 +237,7 @@
return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -245,23 +245,23 @@
return TFM_PLAT_ERR_SUCCESS;
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
diff --git a/platform/ext/target/musca_s1/target_cfg.h b/platform/ext/target/musca_s1/target_cfg.h
index f995216..d42f305 100644
--- a/platform/ext/target/musca_s1/target_cfg.h
+++ b/platform/ext/target/musca_s1/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -71,7 +71,7 @@
{
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/ext/target/sse-200_aws/spm_hal.c b/platform/ext/target/sse-200_aws/spm_hal.c
index 34b2c1c..659f835 100644
--- a/platform/ext/target/sse-200_aws/spm_hal.c
+++ b/platform/ext/target/sse-200_aws/spm_hal.c
@@ -228,7 +228,7 @@
return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
}
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority)
{
uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS);
@@ -236,23 +236,23 @@
return TFM_PLAT_ERR_SUCCESS;
}
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line)
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line)
{
NVIC_ClearPendingIRQ(irq_line);
}
-void tfm_spm_hal_enable_irq(int32_t irq_line)
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line)
{
NVIC_EnableIRQ(irq_line);
}
-void tfm_spm_hal_disable_irq(int32_t irq_line)
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line)
{
NVIC_DisableIRQ(irq_line);
}
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state)
{
uint32_t result;
diff --git a/platform/ext/target/sse-200_aws/target_cfg.h b/platform/ext/target/sse-200_aws/target_cfg.h
index 3abd27d..d3f6ed7 100644
--- a/platform/ext/target/sse-200_aws/target_cfg.h
+++ b/platform/ext/target/sse-200_aws/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 Arm Limited
+ * Copyright (c) 2017-2020 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -72,7 +72,7 @@
{
uint32_t periph_start;
uint32_t periph_limit;
- int16_t periph_ppc_bank;
+ enum ppc_bank_e periph_ppc_bank;
int16_t periph_ppc_loc;
};
diff --git a/platform/include/tfm_spm_hal.h b/platform/include/tfm_spm_hal.h
index 3607753..caed249 100644
--- a/platform/include/tfm_spm_hal.h
+++ b/platform/include/tfm_spm_hal.h
@@ -221,7 +221,7 @@
*
* \return Returns values as specified by the \ref tfm_plat_err_t
*/
-enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(int32_t irq_line,
+enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line,
uint32_t priority);
/**
@@ -229,21 +229,21 @@
*
* \param[in] irq_line The IRQ to clear pending for.
*/
-void tfm_spm_hal_clear_pending_irq(int32_t irq_line);
+void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line);
/**
* \brief Enables an IRQ
*
* \param[in] irq_line The IRQ to be enabled.
*/
-void tfm_spm_hal_enable_irq(int32_t irq_line);
+void tfm_spm_hal_enable_irq(IRQn_Type irq_line);
/**
* \brief Disables an IRQ
*
* \param[in] irq_line The IRQ to be disabled
*/
-void tfm_spm_hal_disable_irq(int32_t irq_line);
+void tfm_spm_hal_disable_irq(IRQn_Type irq_line);
/**
* \brief Set the target state of an IRQ
@@ -257,7 +257,7 @@
* assigned to Non-Secure
*/
enum irq_target_state_t tfm_spm_hal_set_irq_target_state(
- int32_t irq_line,
+ IRQn_Type irq_line,
enum irq_target_state_t target_state);
#ifdef TFM_MULTI_CORE_TOPOLOGY