Mailbox: Optionally cache align NS mailbox struct
The NS mailbox is used to communicate between the SPE and NSPE cores.
Either or both may have a dcache, and the mailbox itself may or may not
be in cacheable memory.
In case the NS mailbox may be cached on one or both sides, introduce
cache alignment where appropriate. The alignment changes can be disabled
by platforms, as they will enlarge the mailbox itself somewhat. This
change means that cache clean and invalidate instructions can be
introduced without erroneously invalidating data that has been changed in
the cache but not yet written to memory.
Signed-off-by: Chris Brand <chris.brand@cypress.com>
Change-Id: I65162684b6a71e65e934530f4bd0293bff6ebddd
diff --git a/docs/configuration/index.rst b/docs/configuration/index.rst
index 520f91f..f6800e8 100644
--- a/docs/configuration/index.rst
+++ b/docs/configuration/index.rst
@@ -266,6 +266,10 @@
+=====================================+===========+============+
|NS_AGENT_MAILBOX_STACK_SIZE | Component | 0x800 |
+-------------------------------------+-----------+------------+
+|MAILBOX_IS_UNCACHED_S | Component | 1 |
++-------------------------------------+-----------+------------+
+|MAILBOX_IS_UNCACHED_NS | Component | 1 |
++-------------------------------------+-----------+------------+
Secure Partition Manager
@@ -293,5 +297,5 @@
--------------
*Copyright (c) 2022,2024, Arm Limited. All rights reserved.*
-*Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company)
+*Copyright (c) 2023-2024 Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation. All rights reserved.*