docs: Fix typos etc
Fix trivial typos, spaces, indentations and other bits in the
documentation.
Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: I4aa6ef65a6caeb73862904033fb29e55dee69f2a
diff --git a/docs/design_docs/software/code_sharing.rst b/docs/design_docs/software/code_sharing.rst
index 5f11bb5..14db411 100644
--- a/docs/design_docs/software/code_sharing.rst
+++ b/docs/design_docs/software/code_sharing.rst
@@ -174,8 +174,8 @@
| Heap |
+-------------------+
-Patching mbedTLS
-================
+Patching Mbed TLS
+=================
In order to share some global function pointers from mbed-crypto that are
related to dynamic memory allocation, their scope must be extended from private
to global. This is needed because some compiler toolchain only extract the
@@ -185,7 +185,7 @@
`lib/ext/mbedcrypto/0002-Enable-crypto-code-sharing-between-independent-binar.patch`
-The patch need to manually applied in the mbedtls repo, if code sharing is
+The patch needs to be manually applied in the Mbed TLS repo, if code sharing is
enabled. The patch has no effect on the functional behaviour of the
cryptographic library, it only extends the scope of some variables.
@@ -304,7 +304,7 @@
version of the shared code. Then new code cannot rely on the shared version.
The changed code and all the other shared code where it is referenced from must
be ignored and the updated version of the functions must be compiled in the
-SPE binary. The mbedTLS library is API compatible with its current version
+SPE binary. The Mbed TLS library is API compatible with its current version
(``v2.24.0``) since the ``mbedtls-2.7.0 release`` (2018-02-03).
To minimise the risk of incompatibility, use the same compiler flags to build
@@ -364,4 +364,4 @@
--------------
-*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*
\ No newline at end of file
+*Copyright (c) 2020-2024, Arm Limited. All rights reserved.*
diff --git a/docs/design_docs/software/hardware_abstraction_layer.rst b/docs/design_docs/software/hardware_abstraction_layer.rst
index bf70d6c..be06dd3 100644
--- a/docs/design_docs/software/hardware_abstraction_layer.rst
+++ b/docs/design_docs/software/hardware_abstraction_layer.rst
@@ -282,7 +282,7 @@
Isolation API
=============
The :term:`PSA-FF-M` defines three isolation levels and a memory access rule to
-provide diverse levels of securitiy. The isolation API provides the functions to
+provide diverse levels of security. The isolation API provides the functions to
implement these requirements.
The Isolation API operates on boundaries. A boundary represents a set of
@@ -480,7 +480,7 @@
**Return Values**
- ``TFM_HAL_SUCCESS`` - the isolation boundary has been set up.
-- ``TFM_HAL_ERROR_GENERIC`` - failed to set upthe isolation boundary.
+- ``TFM_HAL_ERROR_GENERIC`` - failed to set up the isolation boundary.
tfm_hal_memory_check()
^^^^^^^^^^^^^^^^^^^^^^
@@ -916,6 +916,6 @@
--------------
-*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2020-2024, Arm Limited. All rights reserved.*
*Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation. All rights reserved.*
diff --git a/docs/design_docs/software/index.rst b/docs/design_docs/software/index.rst
index 45240ed..cc00ba8 100644
--- a/docs/design_docs/software/index.rst
+++ b/docs/design_docs/software/index.rst
@@ -9,8 +9,8 @@
Hardware Abstraction Layer <hardware_abstraction_layer.rst>
Cooperative Scheduling <tfm_cooperative_scheduling_rules.rst>
Code Templates <tfm_code_generation_with_jinja2.rst>
- Implicit Typecasintg <enum_implicit_casting.rst>
+ Implicit Typecasting <enum_implicit_casting.rst>
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
diff --git a/docs/design_docs/software/tfm_cooperative_scheduling_rules.rst b/docs/design_docs/software/tfm_cooperative_scheduling_rules.rst
index 37270da..0b96f94 100644
--- a/docs/design_docs/software/tfm_cooperative_scheduling_rules.rst
+++ b/docs/design_docs/software/tfm_cooperative_scheduling_rules.rst
@@ -10,7 +10,7 @@
======================
On ArmV8-M CPUs, NSPE and SPE share the same physical processing element(PE). A
-TF-M enabled system need to be able to handle asynchronous events (interrupts)
+TF-M enabled systems need to be able to handle asynchronous events (interrupts)
regardless of current security state of the PE, and that may lead to scheduling
decisions. This introduces significant complexity into TF-M. To keep the
integrity of (NSPE and SPE) schedulers and call paths between NSPE and SPE,
@@ -41,7 +41,7 @@
`Involuntary security state switch`; when the software has no control over the
switch:
-- A NSPE interrupt take control into NSPE from SPE
+- A NSPE interrupt takes control into NSPE from SPE
- A SPE interrupt takes control into SPE from NSPE
`Voluntary security state switch`; when software programmatically makes the
@@ -207,4 +207,4 @@
--------------
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*