LIB: Replace SPM log with tfm_log
Replace the existing SPM log library with the new tfm_log library. This
patch aims to maintain existing behaviour by using a format specifier
which matches the existing implementation.
Change-Id: I5871b5429e4f051fdede87063bfe3ebbe49847f9
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
diff --git a/platform/ext/common/exception_info.c b/platform/ext/common/exception_info.c
index 7ec9460..e7e7a13 100644
--- a/platform/ext/common/exception_info.c
+++ b/platform/ext/common/exception_info.c
@@ -6,7 +6,7 @@
#include <string.h>
#include "tfm_arch.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
/* "exception_info.h" must be the last include because of the IAR pragma */
#include "exception_info.h"
@@ -85,79 +85,79 @@
static void dump_exception_info(bool stack_error,
const struct exception_info_t *ctx)
{
- SPMLOG_DBGMSG("Here is some context for the exception:\r\n");
- SPMLOG_DBGMSGVAL(" EXC_RETURN (LR): ", ctx->EXC_RETURN);
- SPMLOG_DBGMSG(" Exception came from");
+ VERBOSE_RAW("Here is some context for the exception:\n");
+ VERBOSE_RAW(" EXC_RETURN (LR): 0x%08x\n", ctx->EXC_RETURN);
+ VERBOSE_RAW(" Exception came from");
#ifdef TRUSTZONE_PRESENT
if (is_return_secure_stack(ctx->EXC_RETURN)) {
- SPMLOG_DBGMSG(" secure FW in");
+ VERBOSE_RAW(" secure FW in");
} else {
- SPMLOG_DBGMSG(" non-secure FW in");
+ VERBOSE_RAW(" non-secure FW in");
}
#endif
if (is_return_thread_mode(ctx->EXC_RETURN)) {
- SPMLOG_DBGMSG(" thread mode.\r\n");
+ VERBOSE_RAW(" thread mode.\n");
} else {
- SPMLOG_DBGMSG(" handler mode.\r\n");
+ VERBOSE_RAW(" handler mode.\n");
}
- SPMLOG_DBGMSGVAL(" xPSR: ", ctx->xPSR);
- SPMLOG_DBGMSGVAL(" MSP: ", ctx->MSP);
- SPMLOG_DBGMSGVAL(" PSP: ", ctx->PSP);
+ VERBOSE_RAW(" xPSR: 0x%08x\n", ctx->xPSR);
+ VERBOSE_RAW(" MSP: 0x%08x\n", ctx->MSP);
+ VERBOSE_RAW(" PSP: 0x%08x\n", ctx->PSP);
#ifdef TRUSTZONE_PRESENT
- SPMLOG_DBGMSGVAL(" MSP_NS: ", __TZ_get_MSP_NS());
- SPMLOG_DBGMSGVAL(" PSP_NS: ", __TZ_get_PSP_NS());
+ VERBOSE_RAW(" MSP_NS: 0x%08x\n", __TZ_get_MSP_NS());
+ VERBOSE_RAW(" PSP_NS: 0x%08x\n", __TZ_get_PSP_NS());
#endif
- SPMLOG_DBGMSGVAL(" Exception frame at: ", (uint32_t)ctx->EXC_FRAME);
+ VERBOSE_RAW(" Exception frame at: 0x%08x\n", (uint32_t)ctx->EXC_FRAME);
if (stack_error) {
- SPMLOG_DBGMSG(
+ VERBOSE_RAW(
" (Note that the exception frame may be corrupted for this type of error.)\r\n");
}
- SPMLOG_DBGMSGVAL(" R0: ", ctx->EXC_FRAME_COPY[0]);
- SPMLOG_DBGMSGVAL(" R1: ", ctx->EXC_FRAME_COPY[1]);
- SPMLOG_DBGMSGVAL(" R2: ", ctx->EXC_FRAME_COPY[2]);
- SPMLOG_DBGMSGVAL(" R3: ", ctx->EXC_FRAME_COPY[3]);
- SPMLOG_DBGMSGVAL(" R12: ", ctx->EXC_FRAME_COPY[4]);
- SPMLOG_DBGMSGVAL(" LR: ", ctx->EXC_FRAME_COPY[5]);
- SPMLOG_DBGMSGVAL(" PC: ", ctx->EXC_FRAME_COPY[6]);
- SPMLOG_DBGMSGVAL(" xPSR: ", ctx->EXC_FRAME_COPY[7]);
+ VERBOSE_RAW(" R0: 0x%08x\n", ctx->EXC_FRAME_COPY[0]);
+ VERBOSE_RAW(" R1: 0x%08x\n", ctx->EXC_FRAME_COPY[1]);
+ VERBOSE_RAW(" R2: 0x%08x\n", ctx->EXC_FRAME_COPY[2]);
+ VERBOSE_RAW(" R3: 0x%08x\n", ctx->EXC_FRAME_COPY[3]);
+ VERBOSE_RAW(" R12: 0x%08x\n", ctx->EXC_FRAME_COPY[4]);
+ VERBOSE_RAW(" LR: 0x%08x\n", ctx->EXC_FRAME_COPY[5]);
+ VERBOSE_RAW(" PC: 0x%08x\n", ctx->EXC_FRAME_COPY[6]);
+ VERBOSE_RAW(" xPSR: 0x%08x\n", ctx->EXC_FRAME_COPY[7]);
- SPMLOG_DBGMSG(" Callee saved register state:\r\n");
- SPMLOG_DBGMSGVAL(" R4: ", ctx->CALLEE_SAVED_COPY[0]);
- SPMLOG_DBGMSGVAL(" R5: ", ctx->CALLEE_SAVED_COPY[1]);
- SPMLOG_DBGMSGVAL(" R6: ", ctx->CALLEE_SAVED_COPY[2]);
- SPMLOG_DBGMSGVAL(" R7: ", ctx->CALLEE_SAVED_COPY[3]);
- SPMLOG_DBGMSGVAL(" R8: ", ctx->CALLEE_SAVED_COPY[4]);
- SPMLOG_DBGMSGVAL(" R9: ", ctx->CALLEE_SAVED_COPY[5]);
- SPMLOG_DBGMSGVAL(" R10: ", ctx->CALLEE_SAVED_COPY[6]);
- SPMLOG_DBGMSGVAL(" R11: ", ctx->CALLEE_SAVED_COPY[7]);
+ VERBOSE_RAW(" Callee saved register state:\n");
+ VERBOSE_RAW(" R4: 0x%08x\n", ctx->CALLEE_SAVED_COPY[0]);
+ VERBOSE_RAW(" R5: 0x%08x\n", ctx->CALLEE_SAVED_COPY[1]);
+ VERBOSE_RAW(" R6: 0x%08x\n", ctx->CALLEE_SAVED_COPY[2]);
+ VERBOSE_RAW(" R7: 0x%08x\n", ctx->CALLEE_SAVED_COPY[3]);
+ VERBOSE_RAW(" R8: 0x%08x\n", ctx->CALLEE_SAVED_COPY[4]);
+ VERBOSE_RAW(" R9: 0x%08x\n", ctx->CALLEE_SAVED_COPY[5]);
+ VERBOSE_RAW(" R10: 0x%08x\n", ctx->CALLEE_SAVED_COPY[6]);
+ VERBOSE_RAW(" R11: 0x%08x\n", ctx->CALLEE_SAVED_COPY[7]);
#ifdef FAULT_STATUS_PRESENT
- SPMLOG_DBGMSGVAL(" CFSR: ", ctx->CFSR);
- SPMLOG_DBGMSGVAL(" BFSR: ",
+ VERBOSE_RAW(" CFSR: 0x%08x\n", ctx->CFSR);
+ VERBOSE_RAW(" BFSR: ",
(ctx->CFSR & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos);
if (ctx->BFARVALID) {
- SPMLOG_DBGMSGVAL(" BFAR: ", ctx->BFAR);
+ VERBOSE_RAW(" BFAR: 0x%08x\n", ctx->BFAR);
} else {
- SPMLOG_DBGMSG(" BFAR: Not Valid\r\n");
+ VERBOSE_RAW(" BFAR: Not Valid\n");
}
- SPMLOG_DBGMSGVAL(" MMFSR: ",
+ VERBOSE_RAW(" MMFSR: ",
(ctx->CFSR & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos);
if (ctx->MMARVALID) {
- SPMLOG_DBGMSGVAL(" MMFAR: ", ctx->MMFAR);
+ VERBOSE_RAW(" MMFAR: 0x%08x\n", ctx->MMFAR);
} else {
- SPMLOG_DBGMSG(" MMFAR: Not Valid\r\n");
+ VERBOSE_RAW(" MMFAR: Not Valid\n");
}
- SPMLOG_DBGMSGVAL(" UFSR: ",
+ VERBOSE_RAW(" UFSR: 0x%08x\n",
(ctx->CFSR & SCB_CFSR_USGFAULTSR_Msk) >> SCB_CFSR_USGFAULTSR_Pos);
- SPMLOG_DBGMSGVAL(" HFSR: ", ctx->HFSR);
+ VERBOSE_RAW(" HFSR: 0x%08x\n", ctx->HFSR);
#ifdef TRUSTZONE_PRESENT
- SPMLOG_DBGMSGVAL(" SFSR: ", ctx->SFSR);
+ VERBOSE_RAW(" SFSR: 0x%08x\n", ctx->SFSR);
if (ctx->SFARVALID) {
- SPMLOG_DBGMSGVAL(" SFAR: ", ctx->SFAR);
+ VERBOSE_RAW(" SFAR: 0x%08x\n", ctx->SFAR);
} else {
- SPMLOG_DBGMSG(" SFAR: Not Valid\r\n");
+ VERBOSE_RAW(" SFAR: Not Valid\n");
}
#endif
@@ -168,36 +168,36 @@
{
bool stack_error = false;
- SPMLOG_ERRMSG("FATAL ERROR: ");
+ ERROR_RAW("FATAL ERROR: ");
switch (ctx->VECTACTIVE) {
case EXCEPTION_TYPE_HARDFAULT:
- SPMLOG_ERRMSG("HardFault\r\n");
+ ERROR_RAW("HardFault\n");
break;
#ifdef FAULT_STATUS_PRESENT
case EXCEPTION_TYPE_MEMMANAGEFAULT:
- SPMLOG_ERRMSG("MemManage fault\r\n");
+ ERROR_RAW("MemManage fault\n");
stack_error = true;
break;
case EXCEPTION_TYPE_BUSFAULT:
- SPMLOG_ERRMSG("BusFault\r\n");
+ ERROR_RAW("BusFault\n");
stack_error = true;
break;
case EXCEPTION_TYPE_USAGEFAULT:
- SPMLOG_ERRMSG("UsageFault\r\n");
+ ERROR_RAW("UsageFault\n");
stack_error = true;
break;
#ifdef TRUSTZONE_PRESENT
case EXCEPTION_TYPE_SECUREFAULT:
- SPMLOG_ERRMSG("SecureFault\r\n");
+ ERROR_RAW("SecureFault\n");
break;
#endif
#endif
/* Platform specific external interrupt secure handler. */
default:
if (ctx->VECTACTIVE < 16) {
- SPMLOG_ERRMSGVAL("Reserved Exception ", ctx->VECTACTIVE);
+ ERROR_RAW("Reserved Exception 0x%08x\n", ctx->VECTACTIVE);
} else {
- SPMLOG_ERRMSGVAL("Platform external interrupt (IRQn): ", ctx->VECTACTIVE - 16);
+ ERROR_RAW("Platform external interrupt (IRQn): 0x%08x\n", ctx->VECTACTIVE - 16);
}
/* Depends on the platform, assume it may cause stack error */
stack_error = true;
diff --git a/platform/ext/common/provisioning.c b/platform/ext/common/provisioning.c
index c8fa1d9..46a81f9 100644
--- a/platform/ext/common/provisioning.c
+++ b/platform/ext/common/provisioning.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -12,7 +12,7 @@
#include "tfm_plat_otp.h"
#include "tfm_attest_hal.h"
#include "psa/crypto.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include <string.h>
@@ -132,10 +132,10 @@
tfm_plat_otp_read(PLAT_OTP_ID_IAK, sizeof(iak_start), (uint8_t*)&iak_start);
if(iak_start == 0xA4906F6DB254B4A9) {
- SPMLOG_ERRMSG("[WRN]\033[1;31m ");
- SPMLOG_ERRMSG("This device was provisioned with dummy keys. ");
- SPMLOG_ERRMSG("This device is \033[1;1mNOT SECURE");
- SPMLOG_ERRMSG("\033[0m\r\n");
+ ERROR_RAW("[WRN]\033[1;31m ");
+ ERROR_RAW("This device was provisioned with dummy keys. ");
+ ERROR_RAW("This device is \033[1;1mNOT SECURE");
+ ERROR_RAW("\033[0m\n");
}
memset(&iak_start, 0, sizeof(iak_start));
@@ -268,18 +268,18 @@
return err;
}
- SPMLOG_INFMSG("[INF] Beginning TF-M provisioning\r\n");
+ INFO_RAW("[INF] Beginning TF-M provisioning\n");
#ifdef TFM_DUMMY_PROVISIONING
- SPMLOG_ERRMSG("[WRN]\033[1;31m ");
- SPMLOG_ERRMSG("TFM_DUMMY_PROVISIONING is not suitable for production! ");
- SPMLOG_ERRMSG("This device is \033[1;1mNOT SECURE");
- SPMLOG_ERRMSG("\033[0m\r\n");
+ ERROR_RAW("[WRN]\033[1;31m ");
+ ERROR_RAW("TFM_DUMMY_PROVISIONING is not suitable for production! ");
+ ERROR_RAW("This device is \033[1;1mNOT SECURE");
+ ERROR_RAW("\033[0m\n");
#endif /* TFM_DUMMY_PROVISIONING */
if (lcs == PLAT_OTP_LCS_ASSEMBLY_AND_TEST) {
if (assembly_and_test_prov_data.magic != ASSEMBLY_AND_TEST_PROV_DATA_MAGIC) {
- SPMLOG_ERRMSG("No valid ASSEMBLY_AND_TEST provisioning data found\r\n");
+ ERROR_RAW("No valid ASSEMBLY_AND_TEST provisioning data found\n");
return TFM_PLAT_ERR_INVALID_INPUT;
}
@@ -305,7 +305,7 @@
}
if (lcs == PLAT_OTP_LCS_PSA_ROT_PROVISIONING) {
if (psa_rot_prov_data.magic != PSA_ROT_PROV_DATA_MAGIC) {
- SPMLOG_ERRMSG("No valid PSA_ROT provisioning data found\r\n");
+ ERROR_RAW("No valid PSA_ROT provisioning data found\n");
return TFM_PLAT_ERR_INVALID_INPUT;
}
diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
index 1743be9..5c47799 100644
--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
@@ -45,8 +45,8 @@
set(DEFAULT_MCUBOOT_SECURITY_COUNTERS OFF CACHE BOOL "Whether to use the default security counter configuration defined by TF-M project")
# LOG LEVEL
-set(TFM_SPM_LOG_LEVEL TFM_SPM_LOG_LEVEL_INFO CACHE STRING "Set default SPM log level as INFO level")
-set(TFM_PARTITION_LOG_LEVEL LOG_LEVEL_INFO CACHE STRING "Set default Secure Partition log level as INFO level")
+set(TFM_SPM_LOG_LEVEL LOG_LEVEL_INFO CACHE STRING "Set default SPM log level as INFO level")
+set(TFM_PARTITION_LOG_LEVEL LOG_LEVEL_INFO CACHE STRING "Set default Secure Partition log level as INFO level")
# Partition
set(TFM_PARTITION_PLATFORM ON CACHE BOOL "Enable Platform partition")
diff --git a/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_hal.c b/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_hal.c
index 3b10f86..3121cd9 100644
--- a/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_hal.c
+++ b/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_hal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -13,7 +13,7 @@
#include "cmsis.h"
#include "device_definition.h"
#include "tfm_peripherals_def.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include "tfm_pools.h"
#include "rse_comms_protocol.h"
#include <string.h>
@@ -55,19 +55,19 @@
err = mhu_init_sender(&MHU1_SE_TO_HOST_DEV);
if (err != MHU_ERR_NONE) {
- SPMLOG_ERRMSGVAL("[COMMS] RSE to AP_MONITOR MHU driver init failed: ",
+ ERROR_RAW("[COMMS] RSE to AP_MONITOR MHU driver init failed: 0x%08x\n",
err);
return TFM_PLAT_ERR_SYSTEM_ERR;
}
err = mhu_init_receiver(&MHU1_HOST_TO_SE_DEV);
if (err != MHU_ERR_NONE) {
- SPMLOG_ERRMSGVAL("[COMMS] AP_MONITOR to RSE MHU driver init failed: ",
+ ERROR_RAW("[COMMS] AP_MONITOR to RSE MHU driver init failed: 0x%08x\n",
err);
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- SPMLOG_DBGMSG("[COMMS] MHU driver initialized successfully.\r\n");
+ VERBOSE_RAW("[COMMS] MHU driver initialized successfully.\n");
return TFM_PLAT_ERR_SUCCESS;
}
@@ -93,14 +93,14 @@
NVIC_ClearPendingIRQ(source);
if (mhu_err != MHU_ERR_NONE) {
- SPMLOG_DBGMSGVAL("[COMMS] MHU receive failed: ", mhu_err);
+ VERBOSE_RAW("[COMMS] MHU receive failed: 0x%08x\n", mhu_err);
/* Can't respond, since we don't know anything about the message */
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- SPMLOG_DBGMSG("[COMMS] Received message\r\n");
- SPMLOG_DBGMSGVAL("[COMMS] size=", msg_len);
- SPMLOG_DBGMSGVAL("[COMMS] seq_num=", msg.header.seq_num);
+ VERBOSE_RAW("[COMMS] Received message\n");
+ VERBOSE_RAW("[COMMS] size=0x%08x\n", msg_len);
+ VERBOSE_RAW("[COMMS] seq_num=0x%08x\n", msg.header.seq_num);
struct client_request_t *req = tfm_pool_alloc(req_pool);
if (!req) {
@@ -116,7 +116,7 @@
err = rse_protocol_deserialize_msg(req, &msg, msg_len);
if (err != TFM_PLAT_ERR_SUCCESS) {
/* Deserialisation failed, drop message */
- SPMLOG_DBGMSGVAL("[COMMS] Deserialize message failed: ", err);
+ VERBOSE_RAW("[COMMS] Deserialize message failed: 0x%08x\n", err);
goto out_return_err;
}
@@ -164,18 +164,18 @@
err = rse_protocol_serialize_reply(req, &reply, &reply_size);
if (err != TFM_PLAT_ERR_SUCCESS) {
- SPMLOG_DBGMSGVAL("[COMMS] Serialize reply failed: ", err);
+ VERBOSE_RAW("[COMMS] Serialize reply failed: 0x%08x\n", err);
goto out_free_req;
}
mhu_err = mhu_send_data(req->mhu_sender_dev, (uint8_t *)&reply, reply_size);
if (mhu_err != MHU_ERR_NONE) {
- SPMLOG_DBGMSGVAL("[COMMS] MHU send failed: ", mhu_err);
+ VERBOSE_RAW("[COMMS] MHU send failed: 0x%08x\n", mhu_err);
err = TFM_PLAT_ERR_SYSTEM_ERR;
goto out_free_req;
}
- SPMLOG_DBGMSG("[COMMS] Sent reply\r\n");
+ VERBOSE_RAW("[COMMS] Sent reply\n");
out_free_req:
tfm_pool_free(req_pool, req);
@@ -205,7 +205,7 @@
(MHU0_CLIENT_ID_BASE & CLIENT_ID_MHU_BASE_MASK) |
(NS_CLIENT_ID_FLAG_MASK));
} else {
- SPMLOG_DBGMSG("[COMMS] client_id translation failed: invalid owner\r\n");
+ VERBOSE_RAW("[COMMS] client_id translation failed: invalid owner\n");
return 0;
}
}
diff --git a/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_protocol.c b/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_protocol.c
index 94b7995..31dff19 100644
--- a/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_protocol.c
+++ b/platform/ext/target/arm/corstone1000/rse_comms/rse_comms_protocol.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,7 +7,7 @@
#include "rse_comms_protocol.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include <string.h>
enum tfm_plat_err_t rse_protocol_deserialize_msg(
@@ -25,13 +25,13 @@
switch (msg->header.protocol_ver) {
#ifdef RSE_COMMS_PROTOCOL_EMBED_ENABLED
case RSE_COMMS_PROTOCOL_EMBED:
- SPMLOG_DBGMSG("[COMMS] Deserializing as embed message\r\n");
+ VERBOSE_RAW("[COMMS] Deserializing as embed message\n");
return rse_protocol_embed_deserialize_msg(req, &msg->msg.embed,
msg_len - sizeof(struct serialized_rse_comms_header_t));
#endif /* RSE_COMMS_PROTOCOL_EMBED_ENABLED */
#ifdef RSE_COMMS_PROTOCOL_POINTER_ACCESS_ENABLED
case RSE_COMMS_PROTOCOL_POINTER_ACCESS:
- SPMLOG_DBGMSG("[COMMS] Deserializing as pointer_access message\r\n");
+ VERBOSE_RAW("[COMMS] Deserializing as pointer_access message\n");
return rse_protocol_pointer_access_deserialize_msg(req, &msg->msg.pointer_access,
msg_len - sizeof(struct serialized_rse_comms_header_t));
#endif
diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
index 2f5c4f3..3ea1b8e 100644
--- a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -10,7 +10,7 @@
#include "uart_stdout.h"
#include "fwu_agent.h"
#include "watchdog.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
enum tfm_hal_status_t tfm_hal_platform_init(void)
{
@@ -18,12 +18,12 @@
stdio_init();
if (corstone1000_watchdog_init()) {
- SPMLOG_ERRMSG("corstone1000_watchdog_init failed\r\n");
+ ERROR_RAW("corstone1000_watchdog_init failed\n");
return TFM_HAL_ERROR_GENERIC;
}
if (fwu_metadata_init()) {
- SPMLOG_ERRMSG("fwu_metadata_init failed\r\n");
+ ERROR_RAW("fwu_metadata_init failed\n");
return TFM_HAL_ERROR_GENERIC;
}
diff --git a/platform/ext/target/arm/mps3/corstone310/fvp/dma_init.c b/platform/ext/target/arm/mps3/corstone310/fvp/dma_init.c
index 10f13c7..35361e2 100644
--- a/platform/ext/target/arm/mps3/corstone310/fvp/dma_init.c
+++ b/platform/ext/target/arm/mps3/corstone310/fvp/dma_init.c
@@ -80,7 +80,7 @@
dma_err = dma350_set_trigin_nonsecure(&DMA350_DMA0_DEV_S, i);
if(dma_err != DMA350_ERR_NONE)
{
- SPMLOG_ERRMSGVAL("Failed to set the following Trigger input of DMA350_DMA0_DEV_S to NS: ", i);
+ ERROR_RAW("Failed to set the following Trigger input of DMA350_DMA0_DEV_S to NS: 0x%08x\n", i);
return TFM_PLAT_ERR_SYSTEM_ERR;
}
}
diff --git a/platform/ext/target/arm/mps4/common/dma_init.c b/platform/ext/target/arm/mps4/common/dma_init.c
index 6bfae01..b105cdc 100644
--- a/platform/ext/target/arm/mps4/common/dma_init.c
+++ b/platform/ext/target/arm/mps4/common/dma_init.c
@@ -80,7 +80,7 @@
dma_err = dma350_set_trigin_nonsecure(&DMA350_DMA0_DEV_S, i);
if(dma_err != DMA350_ERR_NONE)
{
- SPMLOG_ERRMSGVAL("Failed to set the following Trigger input of DMA350_DMA0_DEV_S to NS: ", i);
+ ERROR_RAW("Failed to set the following Trigger input of DMA350_DMA0_DEV_S to NS: 0x%08x\n", i);
return TFM_PLAT_ERR_SYSTEM_ERR;
}
}
diff --git a/platform/ext/target/arm/rse/common/rse_comms/rse_comms_atu.c b/platform/ext/target/arm/rse/common/rse_comms/rse_comms_atu.c
index ab6c0cc..6daa974 100644
--- a/platform/ext/target/arm/rse/common/rse_comms/rse_comms_atu.c
+++ b/platform/ext/target/arm/rse/common/rse_comms/rse_comms_atu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,7 +7,7 @@
#include "rse_comms_atu.h"
#include "atu_rse_drv.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include "device_definition.h"
#include "platform_base_address.h"
@@ -124,9 +124,9 @@
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- SPMLOG_DBGMSGVAL("[COMMS ATU] Mapping new region: ", region_idx);
- SPMLOG_DBGMSGVAL("[COMMS ATU] Region start: ", region_params->phys_addr);
- SPMLOG_DBGMSGVAL("[COMMS ATU] Region end: ", region_params->phys_addr + region_params->size);
+ VERBOSE_RAW("[COMMS ATU] Mapping new region: 0x%08x\n", region_idx);
+ VERBOSE_RAW("[COMMS ATU] Region start: 0x%08x\n", region_params->phys_addr);
+ VERBOSE_RAW("[COMMS ATU] Region end: 0x%08x\n", region_params->phys_addr + region_params->size);
return TFM_PLAT_ERR_SUCCESS;
}
@@ -174,7 +174,7 @@
if (atu_err) {
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- SPMLOG_DBGMSGVAL("[COMMS ATU] Deallocating region: ", region);
+ VERBOSE_RAW("[COMMS ATU] Deallocating region: 0x%08x\n", region);
}
return TFM_PLAT_ERR_SUCCESS;
@@ -197,7 +197,7 @@
if (atu_err) {
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- SPMLOG_DBGMSGVAL("[COMMS ATU] Deallocating region: ", region_idx);
+ VERBOSE_RAW("[COMMS ATU] Deallocating region: 0x%08x\n", region_idx);
}
}
}
diff --git a/platform/ext/target/cypress/psoc64/driver_ppu.c b/platform/ext/target/cypress/psoc64/driver_ppu.c
index aca15b7..aab5b78 100644
--- a/platform/ext/target/cypress/psoc64/driver_ppu.c
+++ b/platform/ext/target/cypress/psoc64/driver_ppu.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
* limitations under the License.
*/
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include "driver_ppu.h"
#include "pc_config.h"
#include "ppu_config.h"
@@ -222,7 +222,7 @@
#endif
default:
- SPMLOG_ERRMSGVAL("Unexpected peripheral type ", ppu_dev->ppu_type);
+ ERROR_RAW("Unexpected peripheral type 0x%08x\n", ppu_dev->ppu_type);
return CY_PROT_BAD_PARAM;
}
diff --git a/platform/ext/target/cypress/psoc64/driver_smpu.c b/platform/ext/target/cypress/psoc64/driver_smpu.c
index 2c2591b..9216738 100644
--- a/platform/ext/target/cypress/psoc64/driver_smpu.c
+++ b/platform/ext/target/cypress/psoc64/driver_smpu.c
@@ -2,7 +2,7 @@
* Copyright (c) 2019-2022 Cypress Semiconductor Corporation (an Infineon
* company) or an affiliate of Cypress Semiconductor Corporation. All rights
* reserved.
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -28,7 +28,7 @@
#include "region_defs.h"
#include "RTE_Device.h"
#include "smpu_config.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include "tfm_hal_its.h"
#ifdef TFM_PARTITION_PROTECTED_STORAGE
#include "tfm_hal_ps.h"
@@ -290,19 +290,19 @@
static void print_smpu_config(const cy_stc_smpu_cfg_t *slave_config)
{
- SPMLOG_INFMSGVAL(" Address = ", (uintptr_t)slave_config->address);
- SPMLOG_INFMSGVAL(" Size (bytes) = ",
+ INFO_RAW(" Address = 0x%08x\n", (uintptr_t)slave_config->address);
+ INFO_RAW(" Size (bytes) = 0x%08x\n",
REGIONSIZE_TO_BYTES(slave_config->regionSize));
if (slave_config->subregions == ALL_ENABLED) {
- SPMLOG_INFMSG(" All subregions enabled\r\n");
+ INFO_RAW(" All subregions enabled\n");
} else {
- SPMLOG_INFMSGVAL("\tsubregion size (bytes) = ",
+ INFO_RAW("\tsubregion size (bytes) = 0x%08x\n",
REGIONSIZE_TO_BYTES(slave_config->regionSize)/8);
for (int i=0; i<8; i++) {
if (slave_config->subregions & (1<<i)) {
- SPMLOG_INFMSGVAL("\tDisabled subregion ", i);
+ INFO_RAW("\tDisabled subregion 0x%08x\n", i);
} else {
- SPMLOG_INFMSGVAL("\tEnabled subregion ", i);
+ INFO_RAW("\tEnabled subregion 0x%08x\n", i);
}
}
}
@@ -343,30 +343,30 @@
uint32_t subregions;
if (CY_PROT_SUCCESS == get_region(smpu, &base, &size)) {
- SPMLOG_INFMSGVAL(" Wanted address = ", base);
- SPMLOG_INFMSGVAL(" Wanted size (bytes) = ", size);
+ INFO_RAW(" Wanted address = 0x%08x\n", base);
+ INFO_RAW(" Wanted size (bytes) = 0x%08x\n", size);
} else {
- SPMLOG_ERRMSG(" Unsupported dynamic SMPU region\r\n");
+ ERROR_RAW(" Unsupported dynamic SMPU region\n");
}
if (SMPU_Read_Region(smpu, &base, &size32, &subregions, NULL) == CY_PROT_SUCCESS) {
- SPMLOG_INFMSGVAL(" Configured address = ", base);
- SPMLOG_INFMSGVAL(" Configured size (bytes) = ", size32);
+ INFO_RAW(" Configured address = 0x%08x\n", base);
+ INFO_RAW(" Configured size (bytes) = 0x%08x\n", size32);
if (subregions == ALL_ENABLED) {
- SPMLOG_INFMSG(" All subregions enabled\r\n");
+ INFO_RAW(" All subregions enabled\n");
} else {
- SPMLOG_INFMSGVAL("\tsubregion size (bytes) = ", size32/8);
+ INFO_RAW("\tsubregion size (bytes) = 0x%08x\n", size32/8);
for (int i=0; i<8; i++) {
if (subregions & (1<<i)) {
- SPMLOG_INFMSGVAL("\tDisabled subregion ", i);
+ INFO_RAW("\tDisabled subregion 0x%08x\n", i);
} else {
- SPMLOG_INFMSGVAL("\tEnabled subregion ", i);
+ INFO_RAW("\tEnabled subregion 0x%08x\n", i);
}
}
}
} else {
- SPMLOG_ERRMSG("SMPU slave is disabled\r\n");
+ ERROR_RAW("SMPU slave is disabled\n");
}
}
@@ -463,13 +463,13 @@
char smpu_str[SMPU_NAME_MAX_SIZE] = {0};
strcpy(smpu_str, smpu_name(smpu_dev));
- SPMLOG_INFMSG(smpu_str);
+ INFO_RAW("%s", smpu_str);
if (is_runtime(smpu_dev)) {
- SPMLOG_INFMSG(" - configured algorithmically.\r\n");
+ INFO_RAW(" - configured algorithmically.\n");
dump_smpu(smpu_dev->smpu);
} else {
- SPMLOG_INFMSG(" - configured at compile time.\r\n");
+ INFO_RAW(" - configured at compile time.\n");
print_smpu_config(&smpu_dev->slave_config);
}
diff --git a/platform/ext/target/cypress/psoc64/target_cfg.c b/platform/ext/target/cypress/psoc64/target_cfg.c
index d376daf..89e4b80 100644
--- a/platform/ext/target/cypress/psoc64/target_cfg.c
+++ b/platform/ext/target/cypress/psoc64/target_cfg.c
@@ -29,7 +29,7 @@
#include "RTE_Device.h"
#include "target_cfg.h"
#include "tfm_plat_defs.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
/* The section names come from the scatter file */
@@ -142,29 +142,29 @@
/* UART clock */
clk_rc = Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
if (clk_rc != CY_SYSCLK_SUCCESS) {
- SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
+ INFO_RAW("WARNING: Failed to configure UART clock\n");
}
clk_rc = Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 108U);
if (clk_rc != CY_SYSCLK_SUCCESS) {
- SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
+ INFO_RAW("WARNING: Failed to configure UART clock\n");
}
clk_rc = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
if (clk_rc != CY_SYSCLK_SUCCESS) {
- SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
+ INFO_RAW("WARNING: Failed to configure UART clock\n");
}
clk_rc = Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
if (clk_rc != CY_SYSCLK_SUCCESS) {
- SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
+ INFO_RAW("WARNING: Failed to configure UART clock\n");
}
/* Secure: TIMER0 clock */
clk_rc = Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 1U);
if (clk_rc != CY_SYSCLK_SUCCESS) {
- SPMLOG_INFMSG("WARNING: Failed to configure timer0 clock\r\n");
+ INFO_RAW("WARNING: Failed to configure timer0 clock\n");
}
/* Non-Secure: TIMER1 clock */
clk_rc = Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 1U);
if (clk_rc != CY_SYSCLK_SUCCESS) {
- SPMLOG_INFMSG("WARNING: Failed to configure timer1 clock\r\n");
+ INFO_RAW("WARNING: Failed to configure timer1 clock\n");
}
Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
@@ -175,7 +175,7 @@
#if defined(TFM_PARTITION_SLIH_TEST) || defined(TFM_PARTITION_FLIH_TEST)
int_rc = Cy_SysInt_Init(&CY_TCPWM_NVIC_CFG_S, TFM_TIMER0_IRQ_Handler);
if (int_rc != CY_SYSINT_SUCCESS) {
- SPMLOG_INFMSG("WARNING: Fail to initialize timer interrupt (IRQ TEST might fail)!\r\n");
+ INFO_RAW("WARNING: Fail to initialize timer interrupt (IRQ TEST might fail)!\n");
}
#endif /* TFM_PARTITION_SLIH_TEST */
@@ -305,12 +305,12 @@
void smpu_print_config(void)
{
- SPMLOG_INFMSG("\r\nSMPU config:\r\n");
- SPMLOG_INFMSGVAL("memory_regions.non_secure_code_start = ",
+ INFO_RAW("\r\nSMPU config:\n");
+ INFO_RAW("memory_regions.non_secure_code_start = 0x%08x\n",
memory_regions.non_secure_code_start);
- SPMLOG_INFMSGVAL("memory_regions.non_secure_partition_base = ",
+ INFO_RAW("memory_regions.non_secure_partition_base = 0x%08x\n",
memory_regions.non_secure_partition_base);
- SPMLOG_INFMSGVAL("memory_regions.non_secure_partition_limit = ",
+ INFO_RAW("memory_regions.non_secure_partition_limit = 0x%08x\n",
memory_regions.non_secure_partition_limit);
size_t n = sizeof(smpu_init_table)/sizeof(smpu_init_table[0]);
diff --git a/platform/ext/target/cypress/psoc64/tfm_hal_multi_core.c b/platform/ext/target/cypress/psoc64/tfm_hal_multi_core.c
index 19db786..db53435 100644
--- a/platform/ext/target/cypress/psoc64/tfm_hal_multi_core.c
+++ b/platform/ext/target/cypress/psoc64/tfm_hal_multi_core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2024, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
* Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -12,17 +12,17 @@
#include "spe_ipc_config.h"
#include "target_cfg.h"
#include "tfm_plat_defs.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include "tfm_hal_multi_core.h"
static enum tfm_plat_err_t handle_boot_wdt(void)
{
/* Update watchdog timer to mark successfull start up of the image */
- SPMLOG_INFMSG("Checking boot watchdog\r\n");
+ INFO_RAW("Checking boot watchdog\n");
if (cy_p64_wdg_is_enabled()) {
cy_p64_wdg_stop();
cy_p64_wdg_free();
- SPMLOG_INFMSG("Disabled boot watchdog\r\n");
+ INFO_RAW("Disabled boot watchdog\n");
}
return TFM_PLAT_ERR_SUCCESS;
@@ -40,10 +40,10 @@
/* The delay is required after Access port was enabled for
* debugger/programmer to connect and set TEST BIT */
Cy_SysLib_Delay(100);
- SPMLOG_INFMSG("Enabled CM4_AP DAP control\r\n");
+ INFO_RAW("Enabled CM4_AP DAP control\n");
}
- SPMLOG_INFMSGVAL("Starting Cortex-M4 at ", start_addr);
+ INFO_RAW("Starting Cortex-M4 at 0x%08x\n", start_addr);
Cy_SysEnableCM4(start_addr);
}
@@ -74,7 +74,7 @@
Cy_IPC_Drv_ReleaseNotify(Cy_IPC_Drv_GetIpcBaseAddress(IPC_RX_CHAN),
IPC_RX_RELEASE_MASK);
if (data == ~IPC_SYNC_MAGIC) {
- SPMLOG_INFMSG("Cores sync success.\r\n");
+ INFO_RAW("Cores sync success.\n");
break;
}
}
diff --git a/platform/ext/target/lairdconnectivity/common/core/plat_test.c b/platform/ext/target/lairdconnectivity/common/core/plat_test.c
index 5d8e3cc..f2296cc 100644
--- a/platform/ext/target/lairdconnectivity/common/core/plat_test.c
+++ b/platform/ext/target/lairdconnectivity/common/core/plat_test.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved.
* Copyright (c) 2021 Laird Connectivity. All rights reserved.
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -31,7 +31,7 @@
#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC)
#include <tfm_platform_api.h>
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#endif
#ifndef RTE_TWIM2
@@ -113,7 +113,7 @@
pal_timer_stop_ns();
int ret = tfm_platform_system_reset();
if (ret) {
- SPMLOG_ERRMSGVAL("Reset failed: ", ret);
+ ERROR_RAW("Reset failed: 0x%08x\n", ret);
}
}
#endif
diff --git a/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c b/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c
index a5df17e..6670419 100644
--- a/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c
+++ b/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c
@@ -6,41 +6,41 @@
#include <string.h>
#include "nrf_exception_info.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include "spu.h"
static struct nrf_exception_info nrf_exc_info;
static void dump_exception_info(struct nrf_exception_info *ctx)
{
- SPMLOG_ERRMSG("Platform Exception:\r\n");
+ ERROR_RAW("Platform Exception:\n");
/* Report which type of violation occured */
if (ctx->events & SPU_EVENT_RAMACCERR) {
- SPMLOG_DBGMSG(" SPU.RAMACCERR\r\n");
+ VERBOSE_RAW(" SPU.RAMACCERR\n");
}
if (ctx->events & SPU_EVENT_PERIPHACCERR) {
- SPMLOG_DBGMSG(" SPU.PERIPHACCERR\r\n");
- SPMLOG_DBGMSGVAL(" Target addr: ", ctx->periphaccerr.address);
+ VERBOSE_RAW(" SPU.PERIPHACCERR\n");
+ VERBOSE_RAW(" Target addr: 0x%08x\n", ctx->periphaccerr.address);
}
if (ctx->events & SPU_EVENT_FLASHACCERR) {
- SPMLOG_DBGMSG(" SPU.FLASHACCERR\r\n");
+ VERBOSE_RAW(" SPU.FLASHACCERR\n");
}
#if MPC_PRESENT
if (ctx->events & MPC_EVENT_MEMACCERR) {
- SPMLOG_DBGMSG(" MPC.MEMACCERR\r\n");
- SPMLOG_DBGMSGVAL(" Target addr: ", ctx->memaccerr.address);
- SPMLOG_DBGMSGVAL(" Access information: ", ctx->memaccerr.info);
- SPMLOG_DBGMSGVAL(" Owner id: ", ctx->memaccerr.info & 0xf);
- SPMLOG_DBGMSGVAL(" Masterport: ", (ctx->memaccerr.info & 0x1f0) >> 4);
- SPMLOG_DBGMSGVAL(" Read: ", (ctx->memaccerr.info >> 12) & 1);
- SPMLOG_DBGMSGVAL(" Write: ", (ctx->memaccerr.info >> 13) & 1);
- SPMLOG_DBGMSGVAL(" Execute: ", (ctx->memaccerr.info >> 14) & 1);
- SPMLOG_DBGMSGVAL(" Secure: ", (ctx->memaccerr.info >> 15) & 1);
- SPMLOG_DBGMSGVAL(" Error source: ", (ctx->memaccerr.info >> 16) & 1);
+ VERBOSE_RAW(" MPC.MEMACCERR\n");
+ VERBOSE_RAW(" Target addr: 0x%08x\n", ctx->memaccerr.address);
+ VERBOSE_RAW(" Access information: 0x%08x\n", ctx->memaccerr.info);
+ VERBOSE_RAW(" Owner id: 0x%08x\n", ctx->memaccerr.info & 0xf);
+ VERBOSE_RAW(" Masterport: 0x%08x\n", (ctx->memaccerr.info & 0x1f0) >> 4);
+ VERBOSE_RAW(" Read: 0x%08x\n", (ctx->memaccerr.info >> 12) & 1);
+ VERBOSE_RAW(" Write: 0x%08x\n", (ctx->memaccerr.info >> 13) & 1);
+ VERBOSE_RAW(" Execute: 0x%08x\n", (ctx->memaccerr.info >> 14) & 1);
+ VERBOSE_RAW(" Secure: 0x%08x\n", (ctx->memaccerr.info >> 15) & 1);
+ VERBOSE_RAW(" Error source: 0x%08x\n", (ctx->memaccerr.info >> 16) & 1);
}
#endif
}
diff --git a/platform/ext/target/nordic_nrf/common/core/plat_test.c b/platform/ext/target/nordic_nrf/common/core/plat_test.c
index b653f3d..f5e3419 100644
--- a/platform/ext/target/nordic_nrf/common/core/plat_test.c
+++ b/platform/ext/target/nordic_nrf/common/core/plat_test.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved.
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -27,7 +27,7 @@
#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC)
#include <tfm_platform_api.h>
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#endif
#ifdef NRF_TIMER10
diff --git a/platform/ext/target/nxp/common/tfm_hal_isolation.c b/platform/ext/target/nxp/common/tfm_hal_isolation.c
index 3d70bc2..73c9f16 100644
--- a/platform/ext/target/nxp/common/tfm_hal_isolation.c
+++ b/platform/ext/target/nxp/common/tfm_hal_isolation.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
* Copyright 2020-2022 NXP. All rights reserved.
* Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon
* company) or an affiliate of Cypress Semiconductor Corporation. All rights
@@ -170,8 +170,8 @@
n_configured_regions++;
#if TARGET_DEBUG_LOG //NXP
- SPMLOG_DBGMSGVAL("Veneers starts from : ", region_cfg.region_base);
- SPMLOG_DBGMSGVAL("Veneers ends at : ", region_cfg.region_base +
+ VERBOSE_RAW("Veneers starts from : 0x%08x\n", region_cfg.region_base);
+ VERBOSE_RAW("Veneers ends at : 0x%08x\n", region_cfg.region_base +
region_cfg.region_limit);
#endif
@@ -192,8 +192,8 @@
n_configured_regions++;
#if TARGET_DEBUG_LOG //NXP
- SPMLOG_DBGMSGVAL("Code section starts from : ", region_cfg.region_base);
- SPMLOG_DBGMSGVAL("Code section ends at : ", region_cfg.region_base +
+ VERBOSE_RAW("Code section starts from : 0x%08x\n", region_cfg.region_base);
+ VERBOSE_RAW("Code section ends at : 0x%08x\n", region_cfg.region_base +
region_cfg.region_limit);
#endif
@@ -214,8 +214,8 @@
n_configured_regions++;
#if TARGET_DEBUG_LOG //NXP
- SPMLOG_DBGMSGVAL("RO APP CODE starts from : ", region_cfg.region_base);
- SPMLOG_DBGMSGVAL("RO APP CODE ends at : ", region_cfg.region_base +
+ VERBOSE_RAW("RO APP CODE starts from : 0x%08x\n", region_cfg.region_base);
+ VERBOSE_RAW("RO APP CODE ends at : 0x%08x\n", region_cfg.region_base +
region_cfg.region_limit);
#endif
@@ -236,8 +236,8 @@
n_configured_regions++;
#if TARGET_DEBUG_LOG //NXP
- SPMLOG_DBGMSGVAL("RW, ZI APP starts from : ", region_cfg.region_base);
- SPMLOG_DBGMSGVAL("RW, ZI APP ends at : ", region_cfg.region_base +
+ VERBOSE_RAW("RW, ZI APP starts from : 0x%08x\n", region_cfg.region_base);
+ VERBOSE_RAW("RW, ZI APP ends at : 0x%08x\n", region_cfg.region_base +
region_cfg.region_limit);
#endif
@@ -256,8 +256,8 @@
n_configured_regions++;
#if TARGET_DEBUG_LOG
- SPMLOG_DBGMSGVAL("NS Data starts from : ", region_cfg.region_base);
- SPMLOG_DBGMSGVAL("NS Data ends at : ", region_cfg.region_base +
+ VERBOSE_RAW("NS Data starts from : 0x%08x\n", region_cfg.region_base);
+ VERBOSE_RAW("NS Data ends at : 0x%08x\n", region_cfg.region_base +
region_cfg.region_limit);
#endif
diff --git a/platform/ext/target/nxp/common/tfm_hal_platform.c b/platform/ext/target/nxp/common/tfm_hal_platform.c
index e7b0810..17b4d62 100644
--- a/platform/ext/target/nxp/common/tfm_hal_platform.c
+++ b/platform/ext/target/nxp/common/tfm_hal_platform.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
* Copyright 2020-2022 NXP. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -14,7 +14,7 @@
#include "fih.h"
#include "region_defs.h"
#include "region.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
@@ -199,7 +199,7 @@
result = CDOG_Init(CDOG, &conf);
if (result != kStatus_Success)
{
- SPMLOG_ERRMSG("[CDOG] Init error.\r\n");
+ ERROR_RAW("[CDOG] Init error.\n");
FIH_PANIC;
}
@@ -210,33 +210,33 @@
{
NVIC_ClearPendingIRQ(CDOG_IRQn);
- SPMLOG_ERRMSG("[CDOG IRQ] ");
+ ERROR_RAW("[CDOG IRQ] ");
if ((CDOG->FLAGS & CDOG_FLAGS_TO_FLAG_MASK))
{
- SPMLOG_ERRMSG("Timeout ");
+ ERROR_RAW("Timeout ");
}
if ((CDOG->FLAGS & CDOG_FLAGS_MISCOM_FLAG_MASK))
{
- SPMLOG_ERRMSG("Miscompare ");
+ ERROR_RAW("Miscompare ");
}
if ((CDOG->FLAGS & CDOG_FLAGS_SEQ_FLAG_MASK))
{
- SPMLOG_ERRMSG("Sequence ");
+ ERROR_RAW("Sequence ");
}
if ((CDOG->FLAGS & CDOG_FLAGS_CNT_FLAG_MASK))
{
- SPMLOG_ERRMSG("Control ");
+ ERROR_RAW("Control ");
}
if ((CDOG->FLAGS & CDOG_FLAGS_STATE_FLAG_MASK))
{
- SPMLOG_ERRMSG("State ");
+ ERROR_RAW("State ");
}
if ((CDOG->FLAGS & CDOG_FLAGS_ADDR_FLAG_MASK))
{
- SPMLOG_ERRMSG("Address ");
+ ERROR_RAW("Address ");
}
- SPMLOG_ERRMSG("fault occured\r\n");
+ ERROR_RAW("fault occured\n");
FIH_PANIC;
}
diff --git a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
index a4bbf92..27dd92b 100644
--- a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
+++ b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c
@@ -24,7 +24,7 @@
#include "region_defs.h"
#include "tfm_plat_defs.h"
#include "utilities.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
extern const struct memory_region_limits memory_regions;
@@ -211,14 +211,14 @@
AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(0x0U); /* Address space: 0x4010_3000 - 0x4010_3FFF */
#if TARGET_DEBUG_LOG
- SPMLOG_DBGMSG("=== [AHB MPC NS] =======\r\n");
- SPMLOG_DBGMSGVAL("NS ROM starts from : ",
+ VERBOSE_RAW("=== [AHB MPC NS] =======\n");
+ VERBOSE_RAW("NS ROM starts from : 0x%08x\n",
memory_regions.non_secure_partition_base);
- SPMLOG_DBGMSGVAL("NS ROM ends at : ",
+ VERBOSE_RAW("NS ROM ends at : 0x%08x\n",
memory_regions.non_secure_partition_base +
memory_regions.non_secure_partition_limit);
- SPMLOG_DBGMSGVAL("NS DATA start from : ", NS_DATA_START);
- SPMLOG_DBGMSGVAL("NS DATA ends at : ", NS_DATA_START + NS_DATA_LIMIT);
+ VERBOSE_RAW("NS DATA start from : 0x%08x\n", NS_DATA_START);
+ VERBOSE_RAW("NS DATA ends at : 0x%08x\n", NS_DATA_START + NS_DATA_LIMIT);
#endif
/* Add barriers to assure the MPC configuration is done before continue
diff --git a/platform/ext/target/stm/common/secure_element/stsafea/se_psa/se_psa.c b/platform/ext/target/stm/common/secure_element/stsafea/se_psa/se_psa.c
index 307b6f2..f0bd1b2 100644
--- a/platform/ext/target/stm/common/secure_element/stsafea/se_psa/se_psa.c
+++ b/platform/ext/target/stm/common/secure_element/stsafea/se_psa/se_psa.c
@@ -28,7 +28,7 @@
#include "string.h"
#include "psa_manifest/pid.h"
#include "tfm_nspm.h"
-#include "tfm_spm_log.h"
+#include "tfm_log.h"
#include "tfm_plat_defs.h"
#include "tfm_plat_crypto_keys.h"
@@ -81,7 +81,7 @@
char trace_buf[500];
len = vsnprintf(trace_buf, sizeof(trace_buf), fmt, args);
- SPMLOG_DBGMSG(trace_buf);
+ VERBOSE_RAW("%s", trace_buf);
return 0;
}
diff --git a/platform/ext/target/stm/stm32h573i_dk/config.cmake b/platform/ext/target/stm/stm32h573i_dk/config.cmake
index dd3de7b..1a6fbd4 100644
--- a/platform/ext/target/stm/stm32h573i_dk/config.cmake
+++ b/platform/ext/target/stm/stm32h573i_dk/config.cmake
@@ -25,8 +25,8 @@
set(PS_CRYPTO_AEAD_ALG PSA_ALG_GCM CACHE STRING "The AEAD algorithm to use for authenticated encryption in Protected Storage")
set(MCUBOOT_FIH_PROFILE LOW CACHE STRING "Fault injection hardening profile [OFF, LOW, MEDIUM, HIGH]")
################################## LOG LEVEL ###########################################
-set(TFM_SPM_LOG_LEVEL TFM_SPM_LOG_LEVEL_INFO CACHE STRING "Set default SPM log level as INFO level")
-set(TFM_PARTITION_LOG_LEVEL LOG_LEVEL_INFO CACHE STRING "Set default Secure Partition log level as INFO level")
+set(TFM_SPM_LOG_LEVEL LOG_LEVEL_INFO CACHE STRING "Set default SPM log level as INFO level")
+set(TFM_PARTITION_LOG_LEVEL LOG_LEVEL_INFO CACHE STRING "Set default Secure Partition log level as INFO level")
set(MCUBOOT_HW_ROLLBACK_PROT ON CACHE BOOL "Enable security counter validation against non-volatile HW counters")
################################## Platform-specific configurations ####################################
set(CONFIG_TFM_USE_TRUSTZONE ON CACHE BOOL "Use TrustZone")
diff --git a/platform/ext/target/stm/stm32wba65i-dk/config.cmake b/platform/ext/target/stm/stm32wba65i-dk/config.cmake
index 543d354..e6058dc 100644
--- a/platform/ext/target/stm/stm32wba65i-dk/config.cmake
+++ b/platform/ext/target/stm/stm32wba65i-dk/config.cmake
@@ -31,8 +31,8 @@
set(TFM_OTP_DEFAULT_PROVIONNING ON CACHE BOOL "OTP AREA provisionning by TFM")
set(DEFAULT_SHARED_DATA ON CACHE BOOL "SHARED_DATA provisionning by TFM")
################################## LOG LEVEL #############################################################
-set(TFM_SPM_LOG_LEVEL TFM_SPM_LOG_LEVEL_DEBUG CACHE STRING "Set default SPM log level as INFO level")
-set(TFM_PARTITION_LOG_LEVEL LOG_LEVEL_VERBOSE CACHE STRING "Set default Secure Partition log level as INFO level")
+set(TFM_SPM_LOG_LEVEL LOG_LEVEL_VERBOSE CACHE STRING "Set default SPM log level as INFO level")
+set(TFM_PARTITION_LOG_LEVEL LOG_LEVEL_VERBOSE CACHE STRING "Set default Secure Partition log level as INFO level")
################################## FIRMWARE_UPDATE #############################################################
set(TFM_PARTITION_FIRMWARE_UPDATE ON CACHE BOOL "Enable firmware update partition")
set(TFM_FWU_BOOTLOADER_LIB "mcuboot" CACHE STRING "Bootloader configure file for Firmware Update partition")